changeset 6eaa041d043e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6eaa041d043e
description:
ARM: Make native trace print out what instruction caused an error.
diffstat:
4 files changed, 22 insertions(+), 7 deletions(-)
src/arch/arm/nativetrace.cc | 15 +++++++++++++++
src/cpu/NativeTrace.py | 4 ++--
src/cpu/nativetrace.cc | 2 +-
src/cpu/nativetrace.hh | 8 ++++----
diffs (116 lines):
diff -r f61a3b66a5f5 -r 6eaa041d043e src/arch/arm/nativetrace.cc
--- a/src/arch/arm/nativetrace.cc Mon Jul 27 00:54:04 2009 -0700
+++ b/src/arch/arm/nativetrace.cc Mon Jul 27 00:54:09 2009 -0700
@@ -86,6 +86,7 @@
nState.update(this);
mState.update(record->getThread());
+ bool errorFound = false;
// Regular int regs
for (int i = 0; i < STATE_NUMVALS; i++) {
if (nState.changed[i] || mState.changed[i]) {
@@ -104,6 +105,7 @@
vergence, regNames[i],
nState.newState[i],
mState.oldState[i], mState.newState[i]);
+ errorFound = true;
} else if (!mState.changed[i]) {
DPRINTF(ExecRegDelta, "%s [%5s] "\
"Native: %#010x => %#010x "\
@@ -111,6 +113,7 @@
vergence, regNames[i],
nState.oldState[i], nState.newState[i],
mState.newState[i]);
+ errorFound = true;
} else if (mState.oldState[i] != nState.oldState[i] ||
mState.newState[i] != nState.newState[i]) {
DPRINTF(ExecRegDelta, "%s [%5s] "\
@@ -119,9 +122,21 @@
vergence, regNames[i],
nState.oldState[i], nState.newState[i],
mState.oldState[i], mState.newState[i]);
+ errorFound = true;
}
}
}
+ if (errorFound) {
+ StaticInstPtr inst = record->getStaticInst();
+ assert(inst);
+ bool ran = true;
+ if (inst->isMicroop()) {
+ ran = false;
+ inst = record->getMacroStaticInst();
+ }
+ assert(inst);
+ record->traceInst(inst, ran);
+ }
}
} /* namespace Trace */
diff -r f61a3b66a5f5 -r 6eaa041d043e src/cpu/NativeTrace.py
--- a/src/cpu/NativeTrace.py Mon Jul 27 00:54:04 2009 -0700
+++ b/src/cpu/NativeTrace.py Mon Jul 27 00:54:09 2009 -0700
@@ -28,9 +28,9 @@
from m5.SimObject import SimObject
from m5.params import *
-from InstTracer import InstTracer
+from ExeTracer import ExeTracer
-class NativeTrace(InstTracer):
+class NativeTrace(ExeTracer):
abstract = True
type = 'NativeTrace'
cxx_class = 'Trace::NativeTrace'
diff -r f61a3b66a5f5 -r 6eaa041d043e src/cpu/nativetrace.cc
--- a/src/cpu/nativetrace.cc Mon Jul 27 00:54:04 2009 -0700
+++ b/src/cpu/nativetrace.cc Mon Jul 27 00:54:09 2009 -0700
@@ -38,7 +38,7 @@
namespace Trace {
NativeTrace::NativeTrace(const Params *p)
- : InstTracer(p)
+ : ExeTracer(p)
{
if (ListenSocket::allDisabled())
fatal("All listeners are disabled!");
diff -r f61a3b66a5f5 -r 6eaa041d043e src/cpu/nativetrace.hh
--- a/src/cpu/nativetrace.hh Mon Jul 27 00:54:04 2009 -0700
+++ b/src/cpu/nativetrace.hh Mon Jul 27 00:54:09 2009 -0700
@@ -37,8 +37,8 @@
#include "base/socket.hh"
#include "base/trace.hh"
#include "base/types.hh"
+#include "cpu/exetrace.hh"
#include "cpu/static_inst.hh"
-#include "sim/insttracer.hh"
class ThreadContext;
@@ -46,7 +46,7 @@
class NativeTrace;
-class NativeTraceRecord : public InstRecord
+class NativeTraceRecord : public ExeTracerRecord
{
protected:
NativeTrace * parent;
@@ -56,7 +56,7 @@
Tick _when, ThreadContext *_thread,
const StaticInstPtr _staticInst, Addr _pc, bool spec,
const StaticInstPtr _macroStaticInst = NULL, MicroPC _upc = 0)
- : InstRecord(_when, _thread, _staticInst, _pc, spec,
+ : ExeTracerRecord(_when, _thread, _staticInst, _pc, spec,
_macroStaticInst, _upc),
parent(_parent)
{
@@ -65,7 +65,7 @@
void dump();
};
-class NativeTrace : public InstTracer
+class NativeTrace : public ExeTracer
{
protected:
int fd;
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