changeset 4836ec6b73a1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4836ec6b73a1
description:
Simple CPU: Make the simple CPU handle the IntRegs trace flag.
diffstat:
1 file changed, 4 insertions(+), 1 deletion(-)
src/cpu/simple_thread.hh | 5 ++++-
diffs (22 lines):
diff -r fbc8d1e996d9 -r 4836ec6b73a1 src/cpu/simple_thread.hh
--- a/src/cpu/simple_thread.hh Wed Jul 29 00:14:43 2009 -0700
+++ b/src/cpu/simple_thread.hh Wed Jul 29 00:15:26 2009 -0700
@@ -262,7 +262,9 @@
{
int flatIndex = isa.flattenIntIndex(reg_idx);
assert(flatIndex < TheISA::NumIntRegs);
- return intRegs[flatIndex];
+ uint64_t regVal = intRegs[flatIndex];
+ DPRINTF(IntRegs, "Reading int reg %d as %#x.\n", reg_idx, regVal);
+ return regVal;
}
FloatReg readFloatReg(int reg_idx)
@@ -283,6 +285,7 @@
{
int flatIndex = isa.flattenIntIndex(reg_idx);
assert(flatIndex < TheISA::NumIntRegs);
+ DPRINTF(IntRegs, "Setting int reg %d to %#x.\n", reg_idx, val);
intRegs[flatIndex] = val;
}
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