changeset e46754b929ca in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e46754b929ca
description:
merge mips fix and statetrace changes
diffstat:
30 files changed, 1086 insertions(+), 138 deletions(-)
src/arch/arm/ArmNativeTrace.py | 37 +
src/arch/arm/SConscript | 3
src/arch/arm/isa.hh | 6
src/arch/arm/isa/decoder.isa | 26 +
src/arch/arm/isa/formats/pred.isa | 6
src/arch/arm/isa/operands.isa | 8
src/arch/arm/linux/linux.hh | 73 ++-
src/arch/arm/linux/process.cc | 10
src/arch/arm/miscregs.hh | 3
src/arch/arm/nativetrace.cc | 183 ++++++++
src/arch/arm/nativetrace.hh | 112 +++++
src/arch/arm/process.cc | 260 +++++++++---
src/arch/mips/mt.hh | 2
src/base/loader/elf_object.cc | 4
src/base/loader/object_file.hh | 3
src/cpu/NativeTrace.py | 4
src/cpu/nativetrace.cc | 2
src/cpu/nativetrace.hh | 8
src/cpu/simple_thread.hh | 5
src/sim/process.cc | 4
src/sim/process.hh | 4
tests/quick/00.hello/ref/arm/linux/simple-atomic/simerr | 4
tests/quick/00.hello/ref/arm/linux/simple-atomic/simout | 9
tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt | 22 -
util/statetrace/Makefile | 31 +
util/statetrace/arch/tracechild_arm.cc | 236 ++++++++++
util/statetrace/arch/tracechild_arm.hh | 113 +++++
util/statetrace/statetrace.cc | 32 +
util/statetrace/tracechild.cc | 12
util/statetrace/tracechild_arch.cc | 2
diffs (truncated from 1697 to 300 lines):
diff -r ed56e2cac9aa -r e46754b929ca src/arch/arm/ArmNativeTrace.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/arm/ArmNativeTrace.py Fri Jul 31 10:40:42 2009 -0400
@@ -0,0 +1,37 @@
+# Copyright (c) 2009 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from m5.SimObject import SimObject
+from m5.params import *
+from NativeTrace import NativeTrace
+
+class ArmNativeTrace(NativeTrace):
+ type = 'ArmNativeTrace'
+ cxx_class = 'Trace::ArmNativeTrace'
+ stop_on_pc_error = Param.Bool(True,
+ "Stop M5 if it and statetrace's pcs are different")
diff -r ed56e2cac9aa -r e46754b929ca src/arch/arm/SConscript
--- a/src/arch/arm/SConscript Fri Jul 31 09:34:29 2009 -0400
+++ b/src/arch/arm/SConscript Fri Jul 31 10:40:42 2009 -0400
@@ -39,11 +39,14 @@
Source('insts/mem.cc')
Source('insts/pred_inst.cc')
Source('insts/static_inst.cc')
+ Source('nativetrace.cc')
Source('pagetable.cc')
Source('tlb.cc')
Source('vtophys.cc')
+ SimObject('ArmNativeTrace.py')
SimObject('ArmTLB.py')
+
TraceFlag('Arm')
if env['FULL_SYSTEM']:
diff -r ed56e2cac9aa -r e46754b929ca src/arch/arm/isa.hh
--- a/src/arch/arm/isa.hh Fri Jul 31 09:34:29 2009 -0400
+++ b/src/arch/arm/isa.hh Fri Jul 31 10:40:42 2009 -0400
@@ -48,7 +48,11 @@
public:
void clear()
{
- // Unknown startup state currently
+ memset(miscRegs, 0, sizeof(miscRegs));
+ CPSR cpsr = 0;
+ cpsr.mode = MODE_USER;
+ miscRegs[MISCREG_CPSR] = cpsr;
+ //XXX We need to initialize the rest of the state.
}
MiscReg
diff -r ed56e2cac9aa -r e46754b929ca src/arch/arm/isa/decoder.isa
--- a/src/arch/arm/isa/decoder.isa Fri Jul 31 09:34:29 2009 -0400
+++ b/src/arch/arm/isa/decoder.isa Fri Jul 31 10:40:42 2009 -0400
@@ -113,8 +113,7 @@
0x1: decode OPCODE {
0x9: BranchExchange::bx({{ }});
0xb: PredOp::clz({{
- unsigned lsb = findLsbSet(Rm);
- Rd = (lsb > 31) ? 32 : lsb;
+ Rd = ((Rm == 0) ? 32 : (31 - findMsbSet(Rm)));
}});
}
0x2: decode OPCODE {
@@ -319,6 +318,10 @@
0x12,0x16,0x1a,0x1e: ArmMacroFMOp::sfm_pw({{ }});
0x13,0x17,0x1b,0x1f: ArmMacroFMOp::lfm_pw({{ }});
}
+ 0xb: decode LOADOP {
+ 0x0: WarnUnimpl::fstmx();
+ 0x1: WarnUnimpl::fldmx();
+ }
}
0x7: decode OPCODE_24 {
0: decode CPNUM {
@@ -417,12 +420,29 @@
}
}
}
+ 0xa: decode MISC_OPCODE {
+ 0x1: decode MEDIA_OPCODE {
+ 0xf: decode RN {
+ 0x0: FloatOp::fmrx_fpsid({{ Rd = Fpsid; }});
+ 0x1: FloatOp::fmrx_fpscr({{ Rd = Fpscr; }});
+ 0x8: FloatOp::fmrx_fpexc({{ Rd = Fpexc; }});
+ }
+ 0xe: decode RN {
+ 0x0: FloatOp::fmxr_fpsid({{ Fpsid = Rd; }});
+ 0x1: FloatOp::fmxr_fpscr({{ Fpscr = Rd; }});
+ 0x8: FloatOp::fmxr_fpexc({{ Fpexc = Rd; }});
+ }
+ }
+ }
}
format PredOp {
// ARM System Call (SoftWare Interrupt)
1: swi({{ if (testPredicate(Cpsr, condCode))
{
- xc->syscall(IMMED_23_0);
+ if (IMMED_23_0)
+ xc->syscall(IMMED_23_0);
+ else
+ xc->syscall(R7);
}
}});
}
diff -r ed56e2cac9aa -r e46754b929ca src/arch/arm/isa/formats/pred.isa
--- a/src/arch/arm/isa/formats/pred.isa Fri Jul 31 09:34:29 2009 -0400
+++ b/src/arch/arm/isa/formats/pred.isa Fri Jul 31 10:40:42 2009 -0400
@@ -105,7 +105,8 @@
def getCcCode(flagtype):
icReg = icImm = iv = ''
if flagtype == "none":
- icReg = icImm = iv = '1'
+ icReg = icImm = 'Cpsr<29:>'
+ iv = 'Cpsr<28:>'
elif flagtype == "add":
icReg = icImm = 'findCarry(32, resTemp, Rn, op2)'
iv = 'findOverflow(32, resTemp, Rn, op2)'
@@ -125,7 +126,8 @@
def getImmCcCode(flagtype):
ivValue = icValue = ''
if flagtype == "none":
- icValue = ivValue = '1'
+ icValue = 'Cpsr<29:>'
+ ivValue = 'Cpsr<28:>'
elif flagtype == "add":
icValue = 'findCarry(32, resTemp, Rn, rotated_imm)'
ivValue = 'findOverflow(32, resTemp, Rn, rotated_imm)'
diff -r ed56e2cac9aa -r e46754b929ca src/arch/arm/isa/operands.isa
--- a/src/arch/arm/isa/operands.isa Fri Jul 31 09:34:29 2009 -0400
+++ b/src/arch/arm/isa/operands.isa Fri Jul 31 10:40:42 2009 -0400
@@ -57,6 +57,7 @@
'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite),
'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite),
+ 'R7': ('IntReg', 'uw', '7', 'IsInteger', 5),
#Destination register for load/store double instructions
'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead,
maybePCWrite),
@@ -81,7 +82,10 @@
'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 40),
'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 41),
- 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 42),
- 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 43),
+ 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', 'IsInteger', 42),
+ 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', 'IsInteger', 43),
+ 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', 'IsInteger', 44),
+ 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 45),
+ 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 46)
}};
diff -r ed56e2cac9aa -r e46754b929ca src/arch/arm/linux/linux.hh
--- a/src/arch/arm/linux/linux.hh Fri Jul 31 09:34:29 2009 -0400
+++ b/src/arch/arm/linux/linux.hh Fri Jul 31 10:40:42 2009 -0400
@@ -66,18 +66,7 @@
//@}
/// For mmap().
- static const unsigned TGT_MAP_ANONYMOUS = 0x800;
-
- //@{
- /// For getsysinfo().
- static const unsigned GSI_PLATFORM_NAME = 103; //!< platform name as string
- static const unsigned GSI_CPU_INFO = 59; //!< CPU information
- static const unsigned GSI_PROC_TYPE = 60; //!< get proc_type
- static const unsigned GSI_MAX_CPU = 30; //!< max # cpu's on this
machine
- static const unsigned GSI_CPUS_IN_BOX = 55; //!< number of CPUs in
system
- static const unsigned GSI_PHYSMEM = 19; //!< Physical memory in KB
- static const unsigned GSI_CLK_TCK = 42; //!< clock freq in Hz
- //@}
+ static const unsigned TGT_MAP_ANONYMOUS = 0x20;
//@{
/// For getrusage().
@@ -87,13 +76,8 @@
//@}
//@{
- /// For setsysinfo().
- static const unsigned SSI_IEEE_FP_CONTROL = 14; //!< ieee_set_fp_control()
- //@}
-
- //@{
/// ioctl() command codes.
- static const unsigned TIOCGETP_ = 0x40067408;
+ static const unsigned TIOCGETP_ = 0x5401;
static const unsigned TIOCSETP_ = 0x80067409;
static const unsigned TIOCSETN_ = 0x8006740a;
static const unsigned TIOCSETC_ = 0x80067411;
@@ -114,15 +98,56 @@
TGT_RLIMIT_DATA = 2,
TGT_RLIMIT_STACK = 3,
TGT_RLIMIT_CORE = 4,
- TGT_RLIMIT_NOFILE = 5,
- TGT_RLIMIT_AS = 6,
- TGT_RLIMIT_RSS = 7,
- TGT_RLIMIT_VMEM = 7,
- TGT_RLIMIT_NPROC = 8,
- TGT_RLIMIT_MEMLOCK = 9,
+ TGT_RLIMIT_RSS = 5,
+ TGT_RLIMIT_NPROC = 6,
+ TGT_RLIMIT_NOFILE = 7,
+ TGT_RLIMIT_MEMLOCK = 8,
+ TGT_RLIMIT_AS = 9,
TGT_RLIMIT_LOCKS = 10
};
+ typedef struct {
+ uint32_t st_dev;
+ uint32_t st_ino;
+ uint16_t st_mode;
+ uint16_t st_nlink;
+ uint16_t st_uid;
+ uint16_t st_gid;
+ uint32_t st_rdev;
+ uint32_t st_size;
+ uint32_t st_blksize;
+ uint32_t st_blocks;
+ uint32_t st_atimeX;
+ uint32_t st_atime_nsec;
+ uint32_t st_mtimeX;
+ uint32_t st_mtime_nsec;
+ uint32_t st_ctimeX;
+ uint32_t st_ctime_nsec;
+ } tgt_stat;
+
+ typedef struct {
+ uint64_t st_dev;
+ uint8_t __pad0[4];
+ uint32_t __st_ino;
+ uint32_t st_mode;
+ uint32_t st_nlink;
+ uint32_t st_uid;
+ uint32_t st_gid;
+ uint64_t st_rdev;
+ uint8_t __pad3[4];
+ int64_t __attribute__ ((aligned (8))) st_size;
+ uint32_t st_blksize;
+ uint64_t __attribute__ ((aligned (8))) st_blocks;
+ uint32_t st_atimeX;
+ uint32_t st_atime_nsec;
+ uint32_t st_mtimeX;
+ uint32_t st_mtime_nsec;
+ uint32_t st_ctimeX;
+ uint32_t st_ctime_nsec;
+ uint64_t st_ino;
+ } tgt_stat64;
+
+
};
#endif
diff -r ed56e2cac9aa -r e46754b929ca src/arch/arm/linux/process.cc
--- a/src/arch/arm/linux/process.cc Fri Jul 31 09:34:29 2009 -0400
+++ b/src/arch/arm/linux/process.cc Fri Jul 31 10:40:42 2009 -0400
@@ -106,7 +106,7 @@
/* 40 */ SyscallDesc("rmdir", unimplementedFunc),
/* 41 */ SyscallDesc("dup", unimplementedFunc),
/* 42 */ SyscallDesc("pipe", unimplementedFunc),
- /* 43 */ SyscallDesc("times", unimplementedFunc),
+ /* 43 */ SyscallDesc("times", ignoreFunc),
/* 44 */ SyscallDesc("prof", unimplementedFunc),
/* 45 */ SyscallDesc("brk", brkFunc),
/* 46 */ SyscallDesc("setgid", unimplementedFunc),
@@ -260,7 +260,7 @@
/* 194 */ SyscallDesc("ftruncate64", unimplementedFunc),
/* 195 */ SyscallDesc("stat64", unimplementedFunc),
/* 196 */ SyscallDesc("lstat64", lstat64Func<ArmLinux>),
- /* 197 */ SyscallDesc("fstat64", fstatFunc<ArmLinux>),
+ /* 197 */ SyscallDesc("fstat64", fstat64Func<ArmLinux>),
/* 198 */ SyscallDesc("lchown", unimplementedFunc),
/* 199 */ SyscallDesc("getuid", getuidFunc),
/* 200 */ SyscallDesc("getgid", getgidFunc),
@@ -418,7 +418,6 @@
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