changeset 9e35cdc95e81 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9e35cdc95e81
description:
Clean up some inconsistencies with Request flags.
diffstat:
4 files changed, 11 insertions(+), 20 deletions(-)
src/arch/arm/tlb.cc | 2 +-
src/arch/sparc/tlb.cc | 2 +-
src/arch/x86/tlb.cc | 4 ++--
src/mem/request.hh | 23 +++++++----------------
diffs (99 lines):
diff -r 50125d42559c -r 9e35cdc95e81 src/arch/arm/tlb.cc
--- a/src/arch/arm/tlb.cc Sat Aug 01 22:50:10 2009 -0700
+++ b/src/arch/arm/tlb.cc Sat Aug 01 22:50:13 2009 -0700
@@ -147,7 +147,7 @@
// or by the TLB entry
if((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
// mark request as uncacheable
- req->setFlags(req->getFlags() | Request::UNCACHEABLE);
+ req->setFlags(Request::UNCACHEABLE);
}
return NoFault;
}
diff -r 50125d42559c -r 9e35cdc95e81 src/arch/sparc/tlb.cc
--- a/src/arch/sparc/tlb.cc Sat Aug 01 22:50:10 2009 -0700
+++ b/src/arch/sparc/tlb.cc Sat Aug 01 22:50:13 2009 -0700
@@ -837,7 +837,7 @@
regAccessOk:
handleMmuRegAccess:
DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
- req->setMmapedIpr(true);
+ req->setFlags(Request::MMAPED_IPR);
req->setPaddr(req->getVaddr());
return NoFault;
};
diff -r 50125d42559c -r 9e35cdc95e81 src/arch/x86/tlb.cc
--- a/src/arch/x86/tlb.cc Sat Aug 01 22:50:10 2009 -0700
+++ b/src/arch/x86/tlb.cc Sat Aug 01 22:50:13 2009 -0700
@@ -197,7 +197,7 @@
panic("CPUID memory space not yet implemented!\n");
} else if (prefix == IntAddrPrefixMSR) {
vaddr = vaddr >> 3;
- req->setMmapedIpr(true);
+ req->setFlags(Request::MMAPED_IPR);
Addr regNum = 0;
switch (vaddr & ~IntAddrPrefixMask) {
case 0x10:
@@ -526,7 +526,7 @@
// space.
assert(!(IOPort & ~0xFFFF));
if (IOPort == 0xCF8 && req->getSize() == 4) {
- req->setMmapedIpr(true);
+ req->setFlags(Request::MMAPED_IPR);
req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
} else if ((IOPort & ~mask(2)) == 0xCFC) {
Addr configAddress =
diff -r 50125d42559c -r 9e35cdc95e81 src/mem/request.hh
--- a/src/mem/request.hh Sat Aug 01 22:50:10 2009 -0700
+++ b/src/mem/request.hh Sat Aug 01 22:50:13 2009 -0700
@@ -347,6 +347,10 @@
return _flags;
}
+ /** Note that unlike other accessors, this function sets *specific
+ flags* (ORs them in); it does not assign its argument to the
+ _flags field. Thus this method should rightly be called
+ setFlags() and not just flags(). */
void
setFlags(Flags flags)
{
@@ -378,21 +382,6 @@
return _flags & ASI_BITS;
}
- /** Accessor function for MMAPED_IPR flag. */
- bool
- isMmapedIpr()
- {
- assert(privateFlags.isSet(VALID_PADDR));
- return _flags.isSet(MMAPED_IPR);
- }
-
- void
- setMmapedIpr(bool r)
- {
- assert(VALID_VADDR);
- _flags.set(MMAPED_IPR);
- }
-
/** Accessor function to check if sc result is valid. */
bool
extraDataValid()
@@ -452,7 +441,8 @@
return _pc;
}
- /** Accessor Function to Check Cacheability. */
+ /** Accessor functions for flags. Note that these are for testing
+ only; setting flags should be done via setFlags(). */
bool isUncacheable() const { return _flags.isSet(UNCACHEABLE); }
bool isInstFetch() const { return _flags.isSet(INST_FETCH); }
bool isPrefetch() const { return _flags.isSet(PREFETCH); }
@@ -460,6 +450,7 @@
bool isLocked() const { return _flags.isSet(LOCKED); }
bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
+ bool isMmapedIpr() const { return _flags.isSet(MMAPED_IPR); }
bool
isMisaligned() const
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