Korey: I was going to fix this in inorder too, but there are two places where Request objects are allocated (tlb_unit.hh and cache_unit.cc) and I wasn't sure why there were two, if both needed to be fixed, or what.
Also, I think with this flag in place we ought to be able to get rid of the tlb_mode setting; the TLB can just look and see whether isInstFetch() is true to decide how to handle the request... does anyone agree or disagree? Steve On Sat, Aug 1, 2009 at 10:51 PM, Steve Reinhardt<[email protected]> wrote: > changeset 7ed8937e375a in /z/repo/m5 > details: http://repo.m5sim.org/m5?cmd=changeset;node=7ed8937e375a > description: > Fix setting of INST_FETCH flag for O3 CPU. > It's still broken in inorder. > Also enhance DPRINTFs in cache and physical memory so we > can see more easily whether it's getting set or not. > > diffstat: > > 6 files changed, 17 insertions(+), 21 deletions(-) > src/cpu/base_dyn_inst.hh | 10 ++++------ > src/cpu/o3/fetch_impl.hh | 6 +++--- > src/cpu/ozone/inorder_back_end.hh | 4 ---- > src/cpu/simple/base.cc | 1 - > src/mem/cache/cache_impl.hh | 5 +++-- > src/mem/physical.cc | 12 +++++++----- > > diffs (151 lines): > > diff -r 9e35cdc95e81 -r 7ed8937e375a src/cpu/base_dyn_inst.hh > --- a/src/cpu/base_dyn_inst.hh Sat Aug 01 22:50:13 2009 -0700 > +++ b/src/cpu/base_dyn_inst.hh Sat Aug 01 22:50:14 2009 -0700 > @@ -857,9 +857,8 @@ > BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) > { > reqMade = true; > - Request *req = new Request(); > - req->setVirt(asid, addr, sizeof(T), flags, this->PC); > - req->setThreadContext(thread->contextId(), threadNumber); > + Request *req = new Request(asid, addr, sizeof(T), flags, this->PC, > + thread->contextId(), threadNumber); > > fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Read); > > @@ -913,9 +912,8 @@ > } > > reqMade = true; > - Request *req = new Request(); > - req->setVirt(asid, addr, sizeof(T), flags, this->PC); > - req->setThreadContext(thread->contextId(), threadNumber); > + Request *req = new Request(asid, addr, sizeof(T), flags, this->PC, > + thread->contextId(), threadNumber); > > fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write); > > diff -r 9e35cdc95e81 -r 7ed8937e375a src/cpu/o3/fetch_impl.hh > --- a/src/cpu/o3/fetch_impl.hh Sat Aug 01 22:50:13 2009 -0700 > +++ b/src/cpu/o3/fetch_impl.hh Sat Aug 01 22:50:14 2009 -0700 > @@ -596,9 +596,9 @@ > // Setup the memReq to do a read of the first instruction's address. > // Set the appropriate read size and flags as well. > // Build request here. > - RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0, > - fetch_PC, cpu->thread[tid]->contextId(), > - tid); > + RequestPtr mem_req = > + new Request(tid, block_PC, cacheBlkSize, Request::INST_FETCH, > + fetch_PC, cpu->thread[tid]->contextId(), tid); > > memReq[tid] = mem_req; > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
