changeset 2529aeaf1a1c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=2529aeaf1a1c
description:
X86: Make conditional moves zero extend their 32 bit destinations
always.
diffstat:
1 file changed, 1 insertion(+), 1 deletion(-)
src/arch/x86/isa/microops/regop.isa | 2 +-
diffs (12 lines):
diff -r fe6165923529 -r 2529aeaf1a1c src/arch/x86/isa/microops/regop.isa
--- a/src/arch/x86/isa/microops/regop.isa Wed Aug 05 03:07:01 2009 -0700
+++ b/src/arch/x86/isa/microops/regop.isa Wed Aug 05 03:07:55 2009 -0700
@@ -639,7 +639,7 @@
class Mov(CondRegOp):
code = 'DestReg = merge(SrcReg1, op2, dataSize)'
- else_code = 'DestReg=DestReg;'
+ else_code = 'DestReg = merge(DestReg, DestReg, dataSize);'
# Shift instructions
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