changeset 2ec6bfc8f9c7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=2ec6bfc8f9c7
description:
X86: Make the qaud width bswap instruction handle the fact that 32 bit
operations zero extend.
diffstat:
1 file changed, 10 insertions(+), 10 deletions(-)
src/arch/x86/isa/insts/general_purpose/data_conversion/endian_conversion.py |
20 +++++-----
diffs (29 lines):
diff -r f3c9335ec2cd -r 2ec6bfc8f9c7
src/arch/x86/isa/insts/general_purpose/data_conversion/endian_conversion.py
---
a/src/arch/x86/isa/insts/general_purpose/data_conversion/endian_conversion.py
Fri Aug 07 10:12:52 2009 -0700
+++
b/src/arch/x86/isa/insts/general_purpose/data_conversion/endian_conversion.py
Fri Aug 07 10:12:58 2009 -0700
@@ -64,15 +64,15 @@
def macroop BSWAP_Q_R
{
roli reg, reg, 8, dataSize=2
- roli reg, reg, 16, dataSize=4
- roli reg, reg, 8, dataSize=2
- roli reg, reg, 32, dataSize=8
- roli reg, reg, 8, dataSize=2
- roli reg, reg, 16, dataSize=4
- roli reg, reg, 8, dataSize=2
+ roli t1, reg, 16, dataSize=4
+ # Top 4 bytes of t1 are now zero
+ roli t1, t1, 8, dataSize=2
+ roli t1, t1, 32, dataSize=8
+ srli t2, reg, 32, dataSize=8
+ roli t2, t2, 8, dataSize=2
+ roli t2, t2, 16, dataSize=4
+ # Top 4 bytes of t2 are now zero
+ roli t2, t2, 8, dataSize=2
+ or reg, t1, t2, dataSize=8
};
'''
-#let {{
-# class BSWAP(Inst):
-# "GenFault ${new UnimpInstFault}"
-#}};
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