changeset e4b8ec60fd4b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e4b8ec60fd4b
description:
X86: Make not taken conditional moves leave the destination alone.
Adjust CMOVcc.
The manuals from both AMD and Intel say that when writing to a 32 bit
destination in 64 bit mode, the upper 32 bits of the register are
filled with
zeros. They also both say that the CMOV instructions leave their
destination
alone when their condition fails. Unfortunately, it seems that CMOV
will zero
extend its destination register whether or not it was supposed to
actually do
a move on both platforms. This seems to be the only case where this
happens,
but it would be hard to say for sure.
diffstat:
2 files changed, 49 insertions(+), 1 deletion(-)
src/arch/x86/isa/insts/general_purpose/data_transfer/conditional_move.py | 48
++++++++++
src/arch/x86/isa/microops/regop.isa | 2
diffs (truncated from 353 to 300 lines):
diff -r fa6d324aa2f9 -r e4b8ec60fd4b
src/arch/x86/isa/insts/general_purpose/data_transfer/conditional_move.py
--- a/src/arch/x86/isa/insts/general_purpose/data_transfer/conditional_move.py
Fri Aug 07 10:13:33 2009 -0700
+++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/conditional_move.py
Sat Aug 08 17:23:19 2009 -0700
@@ -56,12 +56,14 @@
microcode = '''
def macroop CMOVZ_R_R
{
+ mov reg, reg, reg, flags=(nCZF,)
mov reg, reg, regm, flags=(CZF,)
};
def macroop CMOVZ_R_M
{
ld t1, seg, sib, disp
+ mov reg, reg, reg, flags=(nCZF,)
mov reg, reg, t1, flags=(CZF,)
};
@@ -69,17 +71,20 @@
{
rdip t7
ld t1, seg, riprel, disp
+ mov reg, reg, reg, flags=(nCZF,)
mov reg, reg, t1, flags=(CZF,)
};
def macroop CMOVNZ_R_R
{
+ mov reg, reg, reg, flags=(CZF,)
mov reg, reg, regm, flags=(nCZF,)
};
def macroop CMOVNZ_R_M
{
ld t1, seg, sib, disp
+ mov reg, reg, reg, flags=(CZF,)
mov reg, reg, t1, flags=(nCZF,)
};
@@ -87,17 +92,20 @@
{
rdip t7
ld t1, seg, riprel, disp
+ mov reg, reg, reg, flags=(CZF,)
mov reg, reg, t1, flags=(nCZF,)
};
def macroop CMOVB_R_R
{
+ mov reg, reg, reg, flags=(nCCF,)
mov reg, reg, regm, flags=(CCF,)
};
def macroop CMOVB_R_M
{
ld t1, seg, sib, disp
+ mov reg, reg, reg, flags=(nCCF,)
mov reg, reg, t1, flags=(CCF,)
};
@@ -105,17 +113,20 @@
{
rdip t7
ld t1, seg, riprel, disp
+ mov reg, reg, reg, flags=(nCCF,)
mov reg, reg, t1, flags=(CCF,)
};
def macroop CMOVNB_R_R
{
+ mov reg, reg, reg, flags=(CCF,)
mov reg, reg, regm, flags=(nCCF,)
};
def macroop CMOVNB_R_M
{
ld t1, seg, sib, disp
+ mov reg, reg, reg, flags=(CCF,)
mov reg, reg, t1, flags=(nCCF,)
};
@@ -123,17 +134,20 @@
{
rdip t7
ld t1, seg, riprel, disp
+ mov reg, reg, reg, flags=(CCF,)
mov reg, reg, t1, flags=(nCCF,)
};
def macroop CMOVBE_R_R
{
+ mov reg, reg, reg, flags=(nCCvZF,)
mov reg, reg, regm, flags=(CCvZF,)
};
def macroop CMOVBE_R_M
{
ld t1, seg, sib, disp
+ mov reg, reg, reg, flags=(nCCvZF,)
mov reg, reg, t1, flags=(CCvZF,)
};
@@ -141,17 +155,20 @@
{
rdip t7
ld t1, seg, riprel, disp
+ mov reg, reg, reg, flags=(nCCvZF,)
mov reg, reg, t1, flags=(CCvZF,)
};
def macroop CMOVNBE_R_R
{
+ mov reg, reg, reg, flags=(CCvZF,)
mov reg, reg, regm, flags=(nCCvZF,)
};
def macroop CMOVNBE_R_M
{
ld t1, seg, sib, disp
+ mov reg, reg, reg, flags=(CCvZF,)
mov reg, reg, t1, flags=(nCCvZF,)
};
@@ -159,17 +176,20 @@
{
rdip t7
ld t1, seg, riprel, disp
+ mov reg, reg, reg, flags=(CCvZF,)
mov reg, reg, t1, flags=(nCCvZF,)
};
def macroop CMOVS_R_R
{
+ mov reg, reg, reg, flags=(nCSF,)
mov reg, reg, regm, flags=(CSF,)
};
def macroop CMOVS_R_M
{
ld t1, seg, sib, disp
+ mov reg, reg, reg, flags=(nCSF,)
mov reg, reg, t1, flags=(CSF,)
};
@@ -177,17 +197,20 @@
{
rdip t7
ld t1, seg, riprel, disp
+ mov reg, reg, reg, flags=(nCSF,)
mov reg, reg, t1, flags=(CSF,)
};
def macroop CMOVNS_R_R
{
+ mov reg, reg, reg, flags=(CSF,)
mov reg, reg, regm, flags=(nCSF,)
};
def macroop CMOVNS_R_M
{
ld t1, seg, sib, disp
+ mov reg, reg, reg, flags=(CSF,)
mov reg, reg, t1, flags=(nCSF,)
};
@@ -195,17 +218,20 @@
{
rdip t7
ld t1, seg, riprel, disp
+ mov reg, reg, reg, flags=(CSF,)
mov reg, reg, t1, flags=(nCSF,)
};
def macroop CMOVP_R_R
{
+ mov reg, reg, reg, flags=(nCPF,)
mov reg, reg, regm, flags=(CPF,)
};
def macroop CMOVP_R_M
{
ld t1, seg, sib, disp
+ mov reg, reg, reg, flags=(nCPF,)
mov reg, reg, t1, flags=(CPF,)
};
@@ -213,17 +239,20 @@
{
rdip t7
ld t1, seg, riprel, disp
+ mov reg, reg, reg, flags=(nCPF,)
mov reg, reg, t1, flags=(CPF,)
};
def macroop CMOVNP_R_R
{
+ mov reg, reg, reg, flags=(CPF,)
mov reg, reg, regm, flags=(nCPF,)
};
def macroop CMOVNP_R_M
{
ld t1, seg, sib, disp
+ mov reg, reg, reg, flags=(CPF,)
mov reg, reg, t1, flags=(nCPF,)
};
@@ -231,17 +260,20 @@
{
rdip t7
ld t1, seg, riprel, disp
+ mov reg, reg, reg, flags=(CPF,)
mov reg, reg, t1, flags=(nCPF,)
};
def macroop CMOVL_R_R
{
+ mov reg, reg, reg, flags=(nCSxOF,)
mov reg, reg, regm, flags=(CSxOF,)
};
def macroop CMOVL_R_M
{
ld t1, seg, sib, disp
+ mov reg, reg, reg, flags=(nCSxOF,)
mov reg, reg, t1, flags=(CSxOF,)
};
@@ -249,17 +281,20 @@
{
rdip t7
ld t1, seg, riprel, disp
+ mov reg, reg, reg, flags=(nCSxOF,)
mov reg, reg, t1, flags=(CSxOF,)
};
def macroop CMOVNL_R_R
{
+ mov reg, reg, reg, flags=(CSxOF,)
mov reg, reg, regm, flags=(nCSxOF,)
};
def macroop CMOVNL_R_M
{
ld t1, seg, sib, disp
+ mov reg, reg, reg, flags=(CSxOF,)
mov reg, reg, t1, flags=(nCSxOF,)
};
@@ -267,17 +302,20 @@
{
rdip t7
ld t1, seg, riprel, disp
+ mov reg, reg, reg, flags=(CSxOF,)
mov reg, reg, t1, flags=(nCSxOF,)
};
def macroop CMOVLE_R_R
{
+ mov reg, reg, reg, flags=(nCSxOvZF,)
mov reg, reg, regm, flags=(CSxOvZF,)
};
def macroop CMOVLE_R_M
{
ld t1, seg, sib, disp
+ mov reg, reg, reg, flags=(nCSxOvZF,)
mov reg, reg, t1, flags=(CSxOvZF,)
};
@@ -285,17 +323,20 @@
{
rdip t7
ld t1, seg, riprel, disp
+ mov reg, reg, reg, flags=(nCSxOvZF,)
mov reg, reg, t1, flags=(CSxOvZF,)
};
def macroop CMOVNLE_R_R
{
+ mov reg, reg, reg, flags=(CSxOvZF,)
mov reg, reg, regm, flags=(nCSxOvZF,)
};
def macroop CMOVNLE_R_M
{
ld t1, seg, sib, disp
+ mov reg, reg, reg, flags=(CSxOvZF,)
mov reg, reg, t1, flags=(nCSxOvZF,)
};
@@ -303,17 +344,20 @@
{
rdip t7
ld t1, seg, riprel, disp
+ mov reg, reg, reg, flags=(CSxOvZF,)
mov reg, reg, t1, flags=(nCSxOvZF,)
};
def macroop CMOVO_R_R
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