changeset a2306c563df2 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a2306c563df2
description:
SMT atomics modifications:
don't allow enquing from other threads if servicing and atomic for a
thread
diffstat:
3 files changed, 35 insertions(+), 6 deletions(-)
src/mem/ruby/libruby.hh | 5 +++--
src/mem/ruby/system/Sequencer.cc | 31 +++++++++++++++++++++++++++++--
src/mem/ruby/system/Sequencer.hh | 5 +++--
diffs (101 lines):
diff -r 04a90b404da6 -r a2306c563df2 src/mem/ruby/libruby.hh
--- a/src/mem/ruby/libruby.hh Tue Aug 11 15:19:04 2009 -0700
+++ b/src/mem/ruby/libruby.hh Fri Aug 14 14:06:14 2009 -0500
@@ -31,10 +31,11 @@
uint64_t pc;
RubyRequestType type;
RubyAccessMode access_mode;
+ unsigned proc_id;
RubyRequest() {}
- RubyRequest(uint64_t _paddr, uint8_t* _data, int _len, uint64_t _pc,
RubyRequestType _type, RubyAccessMode _access_mode)
- : paddr(_paddr), data(_data), len(_len), pc(_pc), type(_type),
access_mode(_access_mode)
+ RubyRequest(uint64_t _paddr, uint8_t* _data, int _len, uint64_t _pc,
RubyRequestType _type, RubyAccessMode _access_mode, unsigned _proc_id = 0)
+ : paddr(_paddr), data(_data), len(_len), pc(_pc), type(_type),
access_mode(_access_mode), proc_id(_proc_id)
{}
};
diff -r 04a90b404da6 -r a2306c563df2 src/mem/ruby/system/Sequencer.cc
--- a/src/mem/ruby/system/Sequencer.cc Tue Aug 11 15:19:04 2009 -0700
+++ b/src/mem/ruby/system/Sequencer.cc Fri Aug 14 14:06:14 2009 -0500
@@ -61,6 +61,8 @@
m_instCache_ptr = NULL;
m_dataCache_ptr = NULL;
m_controller = NULL;
+ m_servicing_atomic = -1;
+ m_atomics_counter = 0;
for (size_t i=0; i<argv.size(); i+=2) {
if ( argv[i] == "controller") {
m_controller = RubySystem::getController(argv[i+1]); // args[i] =
"L1Cache"
@@ -342,7 +344,7 @@
}
// Returns true if the sequencer already has a load or store outstanding
-bool Sequencer::isReady(const RubyRequest& request) const {
+bool Sequencer::isReady(const RubyRequest& request) {
// POLINA: check if we are currently flushing the write buffer, if so Ruby
is returned as not ready
// to simulate stalling of the front-end
// Do we stall all the sequencers? If it is atomic instruction - yes!
@@ -357,6 +359,31 @@
return false;
}
+ if (m_servicing_atomic != -1 && m_servicing_atomic != (int)request.proc_id) {
+ assert(m_atomics_counter > 0);
+ return false;
+ }
+ else {
+ if (request.type == RubyRequestType_RMW_Read) {
+ if (m_servicing_atomic == -1) {
+ assert(m_atomics_counter == 0);
+ m_servicing_atomic = (int)request.proc_id;
+ }
+ else {
+ assert(m_servicing_atomic == (int)request.proc_id);
+ }
+ m_atomics_counter++;
+ }
+ else if (request.type == RubyRequestType_RMW_Write) {
+ assert(m_servicing_atomic == (int)request.proc_id);
+ assert(m_atomics_counter > 0);
+ m_atomics_counter--;
+ if (m_atomics_counter == 0) {
+ m_servicing_atomic = -1;
+ }
+ }
+ }
+
return true;
}
@@ -438,7 +465,7 @@
}
Address line_addr(request.paddr);
line_addr.makeLineAddress();
- CacheMsg msg(line_addr, Address(request.paddr), ctype, Address(request.pc),
amtype, request.len, PrefetchBit_No);
+ CacheMsg msg(line_addr, Address(request.paddr), ctype, Address(request.pc),
amtype, request.len, PrefetchBit_No, request.proc_id);
if (Debug::getProtocolTrace()) {
g_system_ptr->getProfiler()->profileTransition("Seq", m_version,
Address(request.paddr),
diff -r 04a90b404da6 -r a2306c563df2 src/mem/ruby/system/Sequencer.hh
--- a/src/mem/ruby/system/Sequencer.hh Tue Aug 11 15:19:04 2009 -0700
+++ b/src/mem/ruby/system/Sequencer.hh Fri Aug 14 14:06:14 2009 -0500
@@ -84,7 +84,7 @@
// called by Tester or Simics
int64_t makeRequest(const RubyRequest & request);
- bool isReady(const RubyRequest& request) const;
+ bool isReady(const RubyRequest& request);
bool empty() const;
void print(ostream& out) const;
@@ -125,7 +125,8 @@
// Global outstanding request count, across all request tables
int m_outstanding_count;
bool m_deadlock_check_scheduled;
-
+ int m_servicing_atomic;
+ int m_atomics_counter;
};
// Output operator declaration
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