changeset 336a194c8500 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=336a194c8500
description:
Made servicing_atomic a counter and added started writes:
a function for setting the flag to indicate that
the rmw_writes started issuing
diffstat:
3 files changed, 70 insertions(+), 59 deletions(-)
src/mem/ruby/slicc_interface/AbstractController.hh | 1
src/mem/ruby/system/Sequencer.cc | 3
src/mem/slicc/symbols/StateMachine.cc | 125 ++++++++++----------
diffs (239 lines):
diff -r d7894bb9c4b5 -r 336a194c8500
src/mem/ruby/slicc_interface/AbstractController.hh
--- a/src/mem/ruby/slicc_interface/AbstractController.hh Fri Aug 14
17:57:54 2009 -0500
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh Sat Aug 15
12:45:11 2009 -0500
@@ -22,6 +22,7 @@
virtual const string getName() const = 0; // return instance name
virtual const MachineType getMachineType() const = 0;
virtual void set_atomic(Address addr) = 0;
+ virtual void started_writes() = 0;
virtual void clear_atomic() = 0;
virtual void print(ostream & out) const = 0;
diff -r d7894bb9c4b5 -r 336a194c8500 src/mem/ruby/system/Sequencer.cc
--- a/src/mem/ruby/system/Sequencer.cc Fri Aug 14 17:57:54 2009 -0500
+++ b/src/mem/ruby/system/Sequencer.cc Sat Aug 15 12:45:11 2009 -0500
@@ -416,6 +416,9 @@
m_dataCache_ptr->clearLocked(line_address(Address(request.paddr)));
}
}
+ if (request.type == RubyRequestType_RMW_Write) {
+ m_controller->started_writes();
+ }
issueRequest(request);
// TODO: issue hardware prefetches here
diff -r d7894bb9c4b5 -r 336a194c8500 src/mem/slicc/symbols/StateMachine.cc
--- a/src/mem/slicc/symbols/StateMachine.cc Fri Aug 14 17:57:54 2009 -0500
+++ b/src/mem/slicc/symbols/StateMachine.cc Sat Aug 15 12:45:11 2009 -0500
@@ -291,6 +291,7 @@
out << " void printConfig(ostream& out) const;" << endl;
out << " void wakeup();" << endl;
out << " void set_atomic(Address addr);" << endl;
+ out << " void started_writes();" << endl;
out << " void clear_atomic();" << endl;
out << " void printStats(ostream& out) const { s_profiler.dumpStats(out);
}" << endl;
out << " void clearStats() { s_profiler.clearStats(); }" << endl;
@@ -301,7 +302,7 @@
out << " int m_" << m_config_parameters->ref(i)->getName() << ";" << endl;
}
if (strncmp(component.c_str(), "L1Cache", 7) == 0) {
- out << " bool servicing_atomic;" << endl;
+ out << " int servicing_atomic;" << endl;
out << " bool started_receiving_writes;" << endl;
out << " Address locked_read_request1;" << endl;
out << " Address locked_read_request2;" << endl;
@@ -416,7 +417,7 @@
out << " : m_name(name)" << endl;
out << "{ " << endl;
if (strncmp(component.c_str(), "L1Cache", 7) == 0) {
- out << " servicing_atomic = false;" << endl;
+ out << " servicing_atomic = 0;" << endl;
out << " started_receiving_writes = false;" << endl;
out << " locked_read_request1 = Address(-1);" << endl;
out << " locked_read_request2 = Address(-1);" << endl;
@@ -728,23 +729,6 @@
string c_code_string = action.lookupPair("c_code");
- // add here:
- if (0/*strncmp(component.c_str(), "L1Cache", 7) == 0*/) {
- if (c_code_string.find("writeCallback") != string::npos) {
- string::size_type pos =
c_code_string.find("(((*m_L1Cache_sequencer_ptr)).writeCallback");
- assert(pos != string::npos);
- string atomics_string = "\n if (servicing_atomic) { \n \
- servicing_atomic = false; \n \
- locked_read_request = Address(-1); \n \
- } \n \
- else if (!servicing_atomic) { \n \
- if (addr == locked_read_request) { \n \
- servicing_atomic = true; \n \
- } \n \
- } \n ";
- c_code_string.insert(pos, atomics_string);
- }
- }
out << c_code_string;
out << "}" << endl;
@@ -811,10 +795,11 @@
assert(pos != string::npos);
string atomics_string = "\n \
if ((((*in_msg_ptr)).m_Type) == CacheRequestType_ATOMIC) { \n \
- if (!servicing_atomic) { \n \
+ if (servicing_atomic == 0) { \n \
if (locked_read_request1 == Address(-1)) { \n \
assert(read_counter == 0); \n \
locked_read_request1 = addr; \n \
+ assert(read_counter == 0); \n \
read_counter++; \n \
} \n \
else if (addr == locked_read_request1) { \n \
@@ -824,48 +809,61 @@
assert(0); // should never be here if servicing one
request at a time \n\
} \n \
} \n \
- else if (addr != locked_read_request1) { \n \
- if (!started_receiving_writes) { \n \
+ else if (!started_receiving_writes) { \n \
+ if (servicing_atomic == 1) { \n \
if (locked_read_request2 == Address(-1)) { \n \
+ assert(locked_read_request1 != Address(-1)); \n \
+ assert(read_counter == 1); \n \
+ locked_read_request2 = addr; \n \
assert(read_counter == 1); \n \
- locked_read_request2 = addr; \n \
read_counter++; \n \
} \n \
- else if (locked_read_request3 == Address(-1)) { \n \
+ else if (addr == locked_read_request2) { \n \
+ ; // do nothing \n\
+ } \n \
+ else { \n \
+ assert(0); // should never be here if servicing one
request at a time \n\
+ } \n \
+ } \n \
+ else if (servicing_atomic == 2) { \n \
+ if (locked_read_request3 == Address(-1)) { \n \
+ assert(locked_read_request1 != Address(-1)); \n \
+ assert(locked_read_request2 != Address(-1)); \n \
+ assert(read_counter == 1); \n \
+ locked_read_request3 = addr; \n \
assert(read_counter == 2); \n \
- locked_read_request3 = addr; \n \
read_counter++; \n \
} \n \
- else if (locked_read_request4 == Address(-1)) { \n \
- assert(read_counter == 3); \n \
- locked_read_request4 = addr; \n \
- read_counter++; \n \
+ else if (addr == locked_read_request3) { \n \
+ ; // do nothing \n\
} \n \
else { \n \
- // reached limit of addresses that could be locked \n \
- // this can happen if there are multiple optimized
consequtive shifts \n \
- assert(0); \n \
+ assert(0); // should never be here if servicing one
request at a time \n\
} \n \
- } \n \
+ } \n \
+ else if (servicing_atomic == 3) { \n \
+ if (locked_read_request4 == Address(-1)) { \n \
+ assert(locked_read_request1 != Address(-1)); \n \
+ assert(locked_read_request2 != Address(-1)); \n \
+ assert(locked_read_request3 != Address(-1)); \n \
+ assert(read_counter == 1); \n \
+ locked_read_request4 = addr; \n \
+ assert(read_counter == 3); \n \
+ read_counter++; \n \
+ } \n \
+ else if (addr == locked_read_request4) { \n \
+ ; // do nothing \n\
+ } \n \
+ else { \n \
+ assert(0); // should never be here if servicing one
request at a time \n\
+ } \n \
+ } \n \
+ else { \n \
+ assert(0); \n \
} \n \
} \n \
- else { \n \
- // if an atomic is followed by non-atomic, reset -> shift
optimization \n \
- // remove this and assert(0) once shifts are resolved \n \
- if (locked_read_request1 != Address(-1)) { \n \
- locked_read_request1 = Address(-1); \n \
- locked_read_request2 = Address(-1); \n \
- locked_read_request3 = Address(-1); \n \
- locked_read_request4 = Address(-1); \n \
- servicing_atomic = false; \n \
- started_receiving_writes = false; \n \
- read_counter = 0; \n \
- } \n \
- } \n \
+ } \n \
";
-
-
-
output.insert(pos, atomics_string);
/*string foo = "// Cannot do anything with this transition, go check next
doable transition (mostly likely of next port)\n";
string::size_type next_pos = output.find(foo, pos);
@@ -888,12 +886,16 @@
out << " if ((((*m_L1Cache_forwardToCache_ptr)).isReady())) {" <<
endl;
out << " const RequestMsg* in_msg_ptr;" << endl;
out << " in_msg_ptr = dynamic_cast<const
RequestMsg*>(((*m_L1Cache_forwardToCache_ptr)).peek());" << endl;
- out << " if ((servicing_atomic && (locked_read_request1 ==
((*in_msg_ptr)).m_Address) || " << endl;
- out << " (locked_read_request2 == ((*in_msg_ptr)).m_Address) ||
(locked_read_request3 == ((*in_msg_ptr)).m_Address) || " << endl;
- out << " (locked_read_request4 == ((*in_msg_ptr)).m_Address)))
{ " << endl;
+ out << " if ((((servicing_atomic == 1) &&
(locked_read_request1 == ((*in_msg_ptr)).m_Address)) || " << endl;
+ out << " ((servicing_atomic == 2) && (locked_read_request1 ==
((*in_msg_ptr)).m_Address || locked_read_request2 ==
((*in_msg_ptr)).m_Address)) || " << endl;
+ out << " ((servicing_atomic == 3) && (locked_read_request1 ==
((*in_msg_ptr)).m_Address || locked_read_request2 == ((*in_msg_ptr)).m_Address
|| locked_read_request3 == ((*in_msg_ptr)).m_Address)) || " << endl;
+ out << " ((servicing_atomic == 4) && (locked_read_request1 ==
((*in_msg_ptr)).m_Address || locked_read_request2 == ((*in_msg_ptr)).m_Address
|| locked_read_request3 == ((*in_msg_ptr)).m_Address || locked_read_request1 ==
((*in_msg_ptr)).m_Address)))) {" << endl;
+// out << " (locked_read_request2 == ((*in_msg_ptr)).m_Address)
|| (locked_read_request3 == ((*in_msg_ptr)).m_Address) || " << endl;
+// out << " (locked_read_request4 ==
((*in_msg_ptr)).m_Address))) { " << endl;
out << " postpone = true;" << endl;
out << " }" << endl;
+
out << " }" << endl;
out << " if (!postpone) {" << endl;
}
@@ -924,18 +926,19 @@
if (strncmp(component.c_str(), "L1Cache", 7) == 0) {
out << "void " << component << "_Controller::set_atomic(Address addr)" <<
endl;
out << "{" << endl;
- out << " if (!servicing_atomic) { " << endl;
- out << " assert(addr == locked_read_request1); " << endl;
- out << " servicing_atomic = true; " << endl;
- out << " }" << endl;
+ out << " servicing_atomic++; " << endl;
+ out << "}" << endl;
+ out << "void " << component << "_Controller::started_writes()" << endl;
+ out << "{" << endl;
+ out << " started_receiving_writes = true; " << endl;
out << "}" << endl;
out << "void " << component << "_Controller::clear_atomic()" << endl;
out << "{" << endl;
- out << " assert(servicing_atomic); " << endl;
- out << " started_receiving_writes = true; " << endl;
+ out << " assert(servicing_atomic > 0); " << endl;
out << " read_counter--; " << endl;
+ out << " servicing_atomic--; " << endl;
out << " if (read_counter == 0) { " << endl;
- out << " servicing_atomic = false; " << endl;
+ out << " servicing_atomic = 0; " << endl;
out << " started_receiving_writes = false; " << endl;
out << " locked_read_request1 = Address(-1); " << endl;
out << " locked_read_request2 = Address(-1); " << endl;
@@ -945,6 +948,10 @@
out << "}" << endl;
}
else {
+ out << "void " << component << "_Controller::started_writes()" << endl;
+ out << "{" << endl;
+ out << " assert(0); " << endl;
+ out << "}" << endl;
out << "void " << component << "_Controller::set_atomic(Address addr)" <<
endl;
out << "{" << endl;
out << " assert(0); " << endl;
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