changeset fa0ea492a075 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=fa0ea492a075
description:
X86: Implement a media square root microop.
diffstat:
1 file changed, 45 insertions(+)
src/arch/x86/isa/microops/mediaop.isa | 45 +++++++++++++++++++++++++++++++++
diffs (53 lines):
diff -r 52b4167056ed -r fa0ea492a075 src/arch/x86/isa/microops/mediaop.isa
--- a/src/arch/x86/isa/microops/mediaop.isa Mon Aug 17 18:33:28 2009 -0700
+++ b/src/arch/x86/isa/microops/mediaop.isa Mon Aug 17 18:34:16 2009 -0700
@@ -529,4 +529,49 @@
}
FpDestReg.uqw = result;
'''
+
+ class Msqrt(MediaOp):
+ def __init__(self, dest, src, \
+ size = None, destSize = None, srcSize = None, ext = None):
+ super(Msqrt, self).__init__(dest, src,\
+ "InstRegIndex(0)", size, destSize, srcSize, ext)
+ code = '''
+ union floatInt
+ {
+ float f;
+ uint32_t i;
+ };
+ union doubleInt
+ {
+ double d;
+ uint64_t i;
+ };
+
+ assert(srcSize == destSize);
+ int size = srcSize;
+ int sizeBits = size * 8;
+ assert(srcSize == 4 || srcSize == 8);
+ int items = (ext & 0x1) ? 1: (sizeof(FloatRegBits) / size);
+ uint64_t result = FpDestReg.uqw;
+
+ for (int i = 0; i < items; i++) {
+ int hiIndex = (i + 1) * sizeBits - 1;
+ int loIndex = (i + 0) * sizeBits;
+ uint64_t argBits = bits(FpSrcReg1.uqw, hiIndex, loIndex);
+
+ if (size == 4) {
+ floatInt fi;
+ fi.i = argBits;
+ fi.f = sqrt(fi.f);
+ argBits = fi.i;
+ } else {
+ doubleInt di;
+ di.i = argBits;
+ di.d = sqrt(di.d);
+ argBits = di.i;
+ }
+ result = insertBits(result, hiIndex, loIndex, argBits);
+ }
+ FpDestReg.uqw = result;
+ '''
}};
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