changeset e8cb266c9451 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e8cb266c9451
description:
        X86: Implement the instructions that convert between forms of floating 
point.

diffstat:

2 files changed, 74 insertions(+), 8 deletions(-)
src/arch/x86/isa/decoder/two_byte_opcodes.isa                                   
                          |    8 -
src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_floating_point.py
 |   74 +++++++++-

diffs (121 lines):

diff -r a34aae12095c -r e8cb266c9451 
src/arch/x86/isa/decoder/two_byte_opcodes.isa
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa     Mon Aug 17 20:04:02 
2009 -0700
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa     Mon Aug 17 20:04:02 
2009 -0700
@@ -500,7 +500,7 @@
                 0x0: decode OPCODE_OP_BOTTOM3 {
                     0x0: Inst::ADDPS(Vo,Wo);
                     0x1: Inst::MULPS(Vo,Wo);
-                    0x2: cvtps2pd_Vo_Wq();
+                    0x2: Inst::CVTPS2PD(Vo,Wq);
                     0x3: Inst::CVTDQ2PS(Vo,Wo);
                     0x4: Inst::SUBPS(Vo,Wo);
                     0x5: Inst::MINPS(Vo,Wo);
@@ -511,7 +511,7 @@
                 0x4: decode OPCODE_OP_BOTTOM3 {
                     0x0: Inst::ADDSS(Vd,Wd);
                     0x1: Inst::MULSS(Vd,Wd);
-                    0x2: cvtss2sd_Vq_Wd();
+                    0x2: Inst::CVTSS2SD(Vq,Wd);
                     0x3: cvttps2dq_Vo_Wo();
                     0x4: Inst::SUBSS(Vd,Wd);
                     0x5: Inst::MINSS(Vd,Wd);
@@ -522,7 +522,7 @@
                 0x1: decode OPCODE_OP_BOTTOM3 {
                     0x0: Inst::ADDPD(Vo,Wo);
                     0x1: Inst::MULPD(Vo,Wo);
-                    0x2: cvtpd2ps_Vo_Wo();
+                    0x2: Inst::CVTPD2PS(Vo,Wo);
                     0x3: cvtps2dq_Vo_Wo();
                     0x4: Inst::SUBPD(Vo,Wo);
                     0x5: Inst::MINPD(Vo,Wo);
@@ -533,7 +533,7 @@
                 0x8: decode OPCODE_OP_BOTTOM3 {
                     0x0: Inst::ADDSD(Vq,Wq);
                     0x1: Inst::MULSD(Vq,Wq);
-                    0x2: cvtsd2ss_Vd_Wq();
+                    0x2: Inst::CVTSD2SS(Vd,Wq);
                     0x4: Inst::SUBSD(Vq,Wq);
                     0x5: Inst::MINSD(Vq,Wq);
                     0x6: Inst::DIVSD(Vq,Wq);
diff -r a34aae12095c -r e8cb266c9451 
src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_floating_point.py
--- 
a/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_floating_point.py
 Mon Aug 17 20:04:02 2009 -0700
+++ 
b/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_floating_point.py
 Mon Aug 17 20:04:02 2009 -0700
@@ -54,8 +54,74 @@
 # Authors: Gabe Black
 
 microcode = '''
-# CVTPS2PD
-# CVTPD2PS
-# CVTSS2SD
-# CVTSD2SS
+def macroop CVTSS2SD_XMM_XMM {
+    cvtf2f xmml, xmmlm, destSize=8, srcSize=4, ext=1
+};
+
+def macroop CVTSS2SD_XMM_M {
+    ldfp ufp1, seg, sib, disp, dataSize=8
+    cvtf2f xmml, ufp1, destSize=8, srcSize=4, ext=1
+};
+
+def macroop CVTSS2SD_XMM_P {
+    rdip t7
+    ldfp ufp1, seg, riprel, disp, dataSize=8
+    cvtf2f xmml, ufp1, destSize=8, srcSize=4, ext=1
+};
+
+def macroop CVTSD2SS_XMM_XMM {
+    cvtf2f xmml, xmmlm, destSize=4, srcSize=8, ext=1
+};
+
+def macroop CVTSD2SS_XMM_M {
+    ldfp ufp1, seg, sib, disp, dataSize=8
+    cvtf2f xmml, ufp1, destSize=4, srcSize=8, ext=1
+};
+
+def macroop CVTSD2SS_XMM_P {
+    rdip t7
+    ldfp ufp1, seg, riprel, disp, dataSize=8
+    cvtf2f xmml, ufp1, destSize=4, srcSize=8, ext=1
+};
+
+def macroop CVTPS2PD_XMM_XMM {
+    cvtf2f xmmh, xmmlm, destSize=8, srcSize=4, ext=2
+    cvtf2f xmml, xmmlm, destSize=8, srcSize=4, ext=0
+};
+
+def macroop CVTPS2PD_XMM_M {
+    ldfp ufp1, seg, sib, disp, dataSize=8
+    cvtf2f xmmh, ufp1, destSize=8, srcSize=4, ext=2
+    cvtf2f xmml, ufp1, destSize=8, srcSize=4, ext=0
+};
+
+def macroop CVTPS2PD_XMM_P {
+    rdip t7
+    ldfp ufp1, seg, riprel, disp, dataSize=8
+    cvtf2f xmmh, ufp1, destSize=8, srcSize=4, ext=2
+    cvtf2f xmml, ufp1, destSize=8, srcSize=4, ext=0
+};
+
+def macroop CVTPD2PS_XMM_XMM {
+    cvtf2f xmml, xmmlm, destSize=4, srcSize=8, ext=0
+    cvtf2f xmml, xmmhm, destSize=4, srcSize=8, ext=2
+    lfpimm xmmh, 0
+};
+
+def macroop CVTPD2PS_XMM_M {
+    ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8
+    ldfp ufp2, seg, sib, "DISPLACEMENT + 8", dataSize=8
+    cvtf2f xmml, ufp1, destSize=4, srcSize=8, ext=0
+    cvtf2f xmml, ufp2, destSize=4, srcSize=8, ext=2
+    lfpimm xmmh, 0
+};
+
+def macroop CVTPD2PS_XMM_P {
+    rdip t7
+    ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8
+    ldfp ufp2, seg, riprel, "DISPLACEMENT + 8", dataSize=8
+    cvtf2f xmml, ufp1, destSize=4, srcSize=8, ext=0
+    cvtf2f xmml, ufp2, destSize=4, srcSize=8, ext=2
+    lfpimm xmmh, 0
+};
 '''
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev

Reply via email to