changeset 3d1ea9362fe5 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3d1ea9362fe5
description:
X86: Implement the insert/extract instructions.
diffstat:
3 files changed, 44 insertions(+), 8 deletions(-)
src/arch/x86/isa/decoder/two_byte_opcodes.isa |
8 +--
src/arch/x86/isa/insts/simd128/integer/data_reordering/extract_and_insert.py |
24 +++++++++-
src/arch/x86/isa/insts/simd64/integer/data_reordering/extract_and_insert.py |
20 +++++++-
diffs (85 lines):
diff -r b617e9c8352e -r 3d1ea9362fe5
src/arch/x86/isa/decoder/two_byte_opcodes.isa
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa Mon Aug 17 20:22:56
2009 -0700
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa Mon Aug 17 20:22:56
2009 -0700
@@ -908,8 +908,8 @@
0x0: decode OPCODE_OP_BOTTOM3 {
0x2: WarnUnimpl::cmpccps_Vo_Wo_Ib();
0x3: WarnUnimpl::movnti_Mdq_Gdq();
- 0x4: WarnUnimpl::pinsrw_Pq_Ew_Ib();
- 0x5: WarnUnimpl::pextrw_Gd_PRq_Ib();
+ 0x4: PINSRW(Pq,Ew,Ib);
+ 0x5: PEXTRW(Gd,PRq,Ib);
0x6: WarnUnimpl::shufps_Vps_Wps_Ib();
}
// repe (0xF3)
@@ -920,8 +920,8 @@
// operand size (0x66)
0x1: decode OPCODE_OP_BOTTOM3 {
0x2: WarnUnimpl::cmpccpd_Vo_Wo_Ib();
- 0x4: WarnUnimpl::pinsrw_Vdw_Ew_Ib();
- 0x5: WarnUnimpl::pextrw_Gd_VRdq_Ib();
+ 0x4: PINSRW(Vdw,Ew,Ib);
+ 0x5: PEXTRW(Gd,VRdq,Ib);
0x6: WarnUnimpl::shufpd_Vpd_Wpd_Ib();
default: UD2();
}
diff -r b617e9c8352e -r 3d1ea9362fe5
src/arch/x86/isa/insts/simd128/integer/data_reordering/extract_and_insert.py
---
a/src/arch/x86/isa/insts/simd128/integer/data_reordering/extract_and_insert.py
Mon Aug 17 20:22:56 2009 -0700
+++
b/src/arch/x86/isa/insts/simd128/integer/data_reordering/extract_and_insert.py
Mon Aug 17 20:22:56 2009 -0700
@@ -54,6 +54,26 @@
# Authors: Gabe Black
microcode = '''
-# PEXTRW
-# PINSRW
+def macroop PEXTRW_R_XMM_I {
+ mov2int reg, xmmlm, "IMMEDIATE & mask(3)", size=2, ext=1
+ mov2int reg, xmmhm, "IMMEDIATE & mask(3)", size=2, ext=1
+};
+
+def macroop PINSRW_XMM_R_I {
+ mov2fp xmml, regm, "IMMEDIATE & mask(3)", size=2, ext=1
+ mov2fp xmmh, regm, "IMMEDIATE & mask(3)", size=2, ext=1
+};
+
+def macroop PINSRW_XMM_M_I {
+ ld t1, seg, sib, disp, dataSize=2
+ mov2fp xmml, t1, "IMMEDIATE & mask(3)", size=2, ext=1
+ mov2fp xmmh, t1, "IMMEDIATE & mask(3)", size=2, ext=1
+};
+
+def macroop PINSRW_XMM_P_I {
+ rdip t7
+ ld t1, seg, riprel, disp, dataSize=2
+ mov2fp xmml, t1, "IMMEDIATE & mask(3)", size=2, ext=1
+ mov2fp xmmh, t1, "IMMEDIATE & mask(3)", size=2, ext=1
+};
'''
diff -r b617e9c8352e -r 3d1ea9362fe5
src/arch/x86/isa/insts/simd64/integer/data_reordering/extract_and_insert.py
---
a/src/arch/x86/isa/insts/simd64/integer/data_reordering/extract_and_insert.py
Mon Aug 17 20:22:56 2009 -0700
+++
b/src/arch/x86/isa/insts/simd64/integer/data_reordering/extract_and_insert.py
Mon Aug 17 20:22:56 2009 -0700
@@ -54,6 +54,22 @@
# Authors: Gabe Black
microcode = '''
-# PEXTRW
-# PINSRW
+def macroop PEXTRW_R_MMX_I {
+ mov2int reg, mmxm, "IMMEDIATE & mask(2)", size=2, ext=0
+};
+
+def macroop PINSRW_MMX_R_I {
+ mov2fp mmx, regm, "IMMEDIATE & mask(2)", size=2, ext=0
+};
+
+def macroop PINSRW_MMX_M_I {
+ ld t1, seg, sib, disp, dataSize=2
+ mov2fp mmx, t1, "IMMEDIATE & mask(2)", size=2, ext=0
+};
+
+def macroop PINSRW_MMX_P_I {
+ rdip t7
+ ld t1, seg, riprel, disp, dataSize=2
+ mov2fp mmx, t1, "IMMEDIATE & mask(2)", size=2, ext=0
+};
'''
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