changeset 4f4318647837 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4f4318647837
description:
X86: Update stats for new SSE instructions.
diffstat:
12 files changed, 84 insertions(+), 84 deletions(-)
tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini | 2
tests/long/10.mcf/ref/x86/linux/simple-atomic/simout | 10 -
tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt | 16 +-
tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini | 2
tests/long/10.mcf/ref/x86/linux/simple-timing/simout | 8 -
tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt | 12 -
tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini | 2
tests/long/70.twolf/ref/x86/linux/simple-atomic/simout | 10 -
tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt | 18 +-
tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini | 2
tests/long/70.twolf/ref/x86/linux/simple-timing/simout | 10 -
tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt | 76 ++++++------
diffs (truncated from 423 to 300 lines):
diff -r 84f7bdc43a4f -r 4f4318647837
tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini Mon Aug 17
20:25:15 2009 -0700
+++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini Mon Aug 17
22:27:30 2009 -0700
@@ -52,7 +52,7 @@
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic
+cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic
egid=100
env=
errout=cerr
diff -r 84f7bdc43a4f -r 4f4318647837
tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout Mon Aug 17
20:25:15 2009 -0700
+++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout Mon Aug 17
22:27:30 2009 -0700
@@ -5,11 +5,11 @@
All Rights Reserved
-M5 compiled Aug 8 2009 12:09:45
-M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch
-M5 started Aug 8 2009 12:09:46
+M5 compiled Aug 17 2009 20:29:57
+M5 revision 84f7bdc43a4f 6605 default qtip tip x86fsdate.patch
+M5 started Aug 17 2009 20:30:53
M5 executing on tater
-command line: build/X86_SE/m5.fast -d
build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py
build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic
+command line: build/X86_SE/m5.opt -d
build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic -re tests/run.py
build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -28,4 +28,4 @@
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 164701785000 because target called exit()
+Exiting @ tick 164701786000 because target called exit()
diff -r 84f7bdc43a4f -r 4f4318647837
tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt Mon Aug 17
20:25:15 2009 -0700
+++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt Mon Aug 17
22:27:30 2009 -0700
@@ -1,17 +1,17 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1102214 #
Simulator instruction rate (inst/s)
-host_mem_usage 332796 #
Number of bytes of host memory used
-host_seconds 244.69 #
Real time elapsed on the host
-host_tick_rate 673115258 #
Simulator tick rate (ticks/s)
+host_inst_rate 635652 #
Simulator instruction rate (inst/s)
+host_mem_usage 347576 #
Number of bytes of host memory used
+host_seconds 424.28 #
Real time elapsed on the host
+host_tick_rate 388188748 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
-sim_insts 269695957 #
Number of instructions simulated
+sim_insts 269695959 #
Number of instructions simulated
sim_seconds 0.164702 #
Number of seconds simulated
-sim_ticks 164701785000 #
Number of ticks simulated
+sim_ticks 164701786000 #
Number of ticks simulated
system.cpu.idle_fraction 0 #
Percentage of idle cycles
system.cpu.not_idle_fraction 1 #
Percentage of non-idle cycles
-system.cpu.numCycles 329403571 #
number of cpu cycles simulated
-system.cpu.num_insts 269695957 #
Number of instructions executed
+system.cpu.numCycles 329403573 #
number of cpu cycles simulated
+system.cpu.num_insts 269695959 #
Number of instructions executed
system.cpu.num_refs 122219131 #
Number of memory references
system.cpu.workload.PROG:num_syscalls 444 #
Number of system calls
diff -r 84f7bdc43a4f -r 4f4318647837
tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini Mon Aug 17
20:25:15 2009 -0700
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini Mon Aug 17
22:27:30 2009 -0700
@@ -152,7 +152,7 @@
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing
+cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
egid=100
env=
errout=cerr
diff -r 84f7bdc43a4f -r 4f4318647837
tests/long/10.mcf/ref/x86/linux/simple-timing/simout
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout Mon Aug 17
20:25:15 2009 -0700
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout Mon Aug 17
22:27:30 2009 -0700
@@ -5,11 +5,11 @@
All Rights Reserved
-M5 compiled Aug 8 2009 12:09:45
-M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch
-M5 started Aug 8 2009 12:13:51
+M5 compiled Aug 17 2009 20:29:57
+M5 revision 84f7bdc43a4f 6605 default qtip tip x86fsdate.patch
+M5 started Aug 17 2009 20:30:53
M5 executing on tater
-command line: build/X86_SE/m5.fast -d
build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py
build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing
+command line: build/X86_SE/m5.opt -d
build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py
build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff -r 84f7bdc43a4f -r 4f4318647837
tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt Mon Aug 17
20:25:15 2009 -0700
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt Mon Aug 17
22:27:30 2009 -0700
@@ -1,11 +1,11 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 617251 #
Simulator instruction rate (inst/s)
-host_mem_usage 340428 #
Number of bytes of host memory used
-host_seconds 436.93 #
Real time elapsed on the host
-host_tick_rate 873410949 #
Simulator tick rate (ticks/s)
+host_inst_rate 395133 #
Simulator instruction rate (inst/s)
+host_mem_usage 355296 #
Number of bytes of host memory used
+host_seconds 682.55 #
Real time elapsed on the host
+host_tick_rate 559113861 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
-sim_insts 269695957 #
Number of instructions simulated
+sim_insts 269695959 #
Number of instructions simulated
sim_seconds 0.381621 #
Number of seconds simulated
sim_ticks 381620562000 #
Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 90779443 #
number of ReadReq accesses(hits+misses)
@@ -200,7 +200,7 @@
system.cpu.l2cache.writebacks 70892 #
number of writebacks
system.cpu.not_idle_fraction 1 #
Percentage of non-idle cycles
system.cpu.numCycles 763241124 #
number of cpu cycles simulated
-system.cpu.num_insts 269695957 #
Number of instructions executed
+system.cpu.num_insts 269695959 #
Number of instructions executed
system.cpu.num_refs 122219131 #
Number of memory references
system.cpu.workload.PROG:num_syscalls 444 #
Number of system calls
diff -r 84f7bdc43a4f -r 4f4318647837
tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini Mon Aug
17 20:25:15 2009 -0700
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini Mon Aug
17 22:27:30 2009 -0700
@@ -52,7 +52,7 @@
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic
+cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic
egid=100
env=
errout=cerr
diff -r 84f7bdc43a4f -r 4f4318647837
tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout Mon Aug 17
20:25:15 2009 -0700
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout Mon Aug 17
22:27:30 2009 -0700
@@ -5,11 +5,11 @@
All Rights Reserved
-M5 compiled Aug 8 2009 12:09:45
-M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch
-M5 started Aug 8 2009 12:09:46
+M5 compiled Aug 17 2009 20:29:57
+M5 revision 84f7bdc43a4f 6605 default qtip tip x86fsdate.patch
+M5 started Aug 17 2009 20:37:58
M5 executing on tater
-command line: build/X86_SE/m5.fast -d
build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py
build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic
+command line: build/X86_SE/m5.opt -d
build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic -re tests/run.py
build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -27,4 +27,4 @@
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 130326747000 because target called exit()
+122 123 124 Exiting @ tick 130427072000 because target called exit()
diff -r 84f7bdc43a4f -r 4f4318647837
tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt Mon Aug 17
20:25:15 2009 -0700
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt Mon Aug 17
22:27:30 2009 -0700
@@ -1,17 +1,17 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1070420 #
Simulator instruction rate (inst/s)
-host_mem_usage 205608 #
Number of bytes of host memory used
-host_seconds 204.81 #
Real time elapsed on the host
-host_tick_rate 636336293 #
Simulator tick rate (ticks/s)
+host_inst_rate 608858 #
Simulator instruction rate (inst/s)
+host_mem_usage 220444 #
Number of bytes of host memory used
+host_seconds 360.40 #
Real time elapsed on the host
+host_tick_rate 361897269 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
-sim_insts 219230323 #
Number of instructions simulated
-sim_seconds 0.130327 #
Number of seconds simulated
-sim_ticks 130326747000 #
Number of ticks simulated
+sim_insts 219430973 #
Number of instructions simulated
+sim_seconds 0.130427 #
Number of seconds simulated
+sim_ticks 130427072000 #
Number of ticks simulated
system.cpu.idle_fraction 0 #
Percentage of idle cycles
system.cpu.not_idle_fraction 1 #
Percentage of non-idle cycles
-system.cpu.numCycles 260653495 #
number of cpu cycles simulated
-system.cpu.num_insts 219230323 #
Number of instructions executed
+system.cpu.numCycles 260854145 #
number of cpu cycles simulated
+system.cpu.num_insts 219430973 #
Number of instructions executed
system.cpu.num_refs 77165298 #
Number of memory references
system.cpu.workload.PROG:num_syscalls 400 #
Number of system calls
diff -r 84f7bdc43a4f -r 4f4318647837
tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini Mon Aug
17 20:25:15 2009 -0700
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini Mon Aug
17 22:27:30 2009 -0700
@@ -152,7 +152,7 @@
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing
+cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing
egid=100
env=
errout=cerr
diff -r 84f7bdc43a4f -r 4f4318647837
tests/long/70.twolf/ref/x86/linux/simple-timing/simout
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout Mon Aug 17
20:25:15 2009 -0700
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout Mon Aug 17
22:27:30 2009 -0700
@@ -5,11 +5,11 @@
All Rights Reserved
-M5 compiled Aug 8 2009 12:09:45
-M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch
-M5 started Aug 8 2009 12:09:46
+M5 compiled Aug 17 2009 20:29:57
+M5 revision 84f7bdc43a4f 6605 default qtip tip x86fsdate.patch
+M5 started Aug 17 2009 20:42:16
M5 executing on tater
-command line: build/X86_SE/m5.fast -d
build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py
build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing
+command line: build/X86_SE/m5.opt -d
build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re tests/run.py
build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -27,4 +27,4 @@
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 250945548000 because target called exit()
+122 123 124 Exiting @ tick 250961789000 because target called exit()
diff -r 84f7bdc43a4f -r 4f4318647837
tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt Mon Aug 17
20:25:15 2009 -0700
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt Mon Aug 17
22:27:30 2009 -0700
@@ -1,17 +1,17 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 632486 #
Simulator instruction rate (inst/s)
-host_mem_usage 213180 #
Number of bytes of host memory used
-host_seconds 346.62 #
Real time elapsed on the host
-host_tick_rate 723985351 #
Simulator tick rate (ticks/s)
+host_inst_rate 489241 #
Simulator instruction rate (inst/s)
+host_mem_usage 228040 #
Number of bytes of host memory used
+host_seconds 448.51 #
Real time elapsed on the host
+host_tick_rate 559541126 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
-sim_insts 219230323 #
Number of instructions simulated
-sim_seconds 0.250946 #
Number of seconds simulated
-sim_ticks 250945548000 #
Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 56649600 #
number of ReadReq accesses(hits+misses)
+sim_insts 219430973 #
Number of instructions simulated
+sim_seconds 0.250962 #
Number of seconds simulated
+sim_ticks 250961789000 #
Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 56682001 #
number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 55873.040752
# average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52873.040752
# average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 56649281 #
number of ReadReq hits
+system.cpu.dcache.ReadReq_hits 56681682 #
number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 17823500 #
number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000006 #
miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 319 #
number of ReadReq misses
@@ -30,16 +30,16 @@
system.cpu.dcache.WriteReq_mshr_misses 1601 #
number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
# average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value
# average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 40740.989968 #
Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 40758.097149 #
Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 #
number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 #
number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0
# number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0
# number of cycles access was blocked
system.cpu.dcache.cache_copies 0 #
number of cache copies performed
-system.cpu.dcache.demand_accesses 77165329 #
number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses 77197730 #
number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 55978.906250 #
average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 52978.906250
# average overall mshr miss latency
-system.cpu.dcache.demand_hits 77163409 #
number of demand (read+write) hits
+system.cpu.dcache.demand_hits 77195810 #
number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 107479500 #
number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000025 #
miss rate for demand accesses
system.cpu.dcache.demand_misses 1920 #
number of demand (read+write) misses
@@ -50,11 +50,11 @@
system.cpu.dcache.fast_writes 0 #
number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 #
Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 77165329 #
number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses 77197730 #
number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 55978.906250
# average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 52978.906250
# average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 77163409 #
number of overall hits
+system.cpu.dcache.overall_hits 77195810 #
number of overall hits
system.cpu.dcache.overall_miss_latency 107479500 #
number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000025 #
miss rate for overall accesses
system.cpu.dcache.overall_misses 1920 #
number of overall misses
@@ -67,18 +67,18 @@
system.cpu.dcache.replacements 27 #
number of replacements
system.cpu.dcache.sampled_refs 1894 #
Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1362.582602 #
Cycle average of tags in use
-system.cpu.dcache.total_refs 77163435 #
Total number of references to valid blocks.
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