changeset 369b61762d7b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=369b61762d7b
description:
[mq]: MOESI_patch
diffstat:
1 file changed, 36 insertions(+), 13 deletions(-)
src/mem/protocol/MOESI_CMP_directory-dir.sm | 49 +++++++++++++++++++--------
diffs (109 lines):
diff -r c7fb413a369f -r 369b61762d7b src/mem/protocol/MOESI_CMP_directory-dir.sm
--- a/src/mem/protocol/MOESI_CMP_directory-dir.sm Fri Aug 28 15:09:41
2009 -0500
+++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm Mon Aug 31 16:38:22
2009 -0500
@@ -405,6 +405,14 @@
}
}
+ action(p_writeFwdDataToMemory, "p", desc="Write Response data to memory") {
+ peek(unblockNetwork_in, ResponseMsg) {
+ directory[in_msg.Address].DataBlk := in_msg.DataBlk;
+ DEBUG_EXPR(in_msg.Address);
+ DEBUG_EXPR(in_msg.DataBlk);
+ }
+ }
+
action(ll_checkDataInMemory, "\ld", desc="Check PUTX/PUTO data is same as in
the memory") {
peek(unblockNetwork_in, ResponseMsg) {
assert(in_msg.Dirty == false);
@@ -506,14 +514,31 @@
}
action(a_sendDMAAck, "\a", desc="Send DMA Ack that write completed, along
with Inv Ack count") {
- peek(memQueue_in, MemoryMsg) {
+ peek(requestQueue_in, RequestMsg) {
enqueue(responseNetwork_out, ResponseMsg, latency="1") {
out_msg.Address := address;
out_msg.Sender := machineID;
out_msg.SenderMachine := MachineType:Directory;
- out_msg.Destination.add(in_msg.OriginalRequestorMachId);
+ out_msg.Destination.add(in_msg.Requestor);
out_msg.DataBlk := in_msg.DataBlk;
- out_msg.Acks := in_msg.Acks;
+ out_msg.Acks := directory[address].Sharers.count(); // for dma requests
+ out_msg.Type := CoherenceResponseType:DMA_ACK;
+ out_msg.MessageSize := MessageSizeType:Writeback_Control;
+ }
+ }
+ }
+
+ action(a_sendDMAAck2, "\aa", desc="Send DMA Ack that write completed, along
with Inv Ack count") {
+ peek(unblockNetwork_in, ResponseMsg) {
+ enqueue(responseNetwork_out, ResponseMsg, latency="1") {
+ out_msg.Address := address;
+ out_msg.Sender := machineID;
+ out_msg.SenderMachine := MachineType:Directory;
+ if (TBEs.isPresent(address)) {
+ out_msg.Destination.add(TBEs[address].Requestor);
+ }
+ out_msg.DataBlk := in_msg.DataBlk;
+ out_msg.Acks := directory[address].Sharers.count(); // for dma requests
out_msg.Type := CoherenceResponseType:DMA_ACK;
out_msg.MessageSize := MessageSizeType:Writeback_Control;
}
@@ -560,8 +585,9 @@
i_popIncomingRequestQueue;
}
- transition(I, DMA_WRITE, XI_M) {
+ transition(I, DMA_WRITE, XI_U) {
qw_queueMemoryWBRequest2;
+ a_sendDMAAck; // ack count may be zero
l_writeDMADataToMemory;
i_popIncomingRequestQueue;
}
@@ -571,11 +597,6 @@
q_popMemQueue;
}
- transition(XI_M, Memory_Ack, XI_U) {
- a_sendDMAAck; // ack count may be zero
- q_popMemQueue;
- }
-
transition(XI_U, Exclusive_Unblock, I) {
cc_clearSharers;
c_clearOwner;
@@ -594,8 +615,9 @@
i_popIncomingRequestQueue;
}
- transition(S, DMA_WRITE, XI_M) {
+ transition(S, DMA_WRITE, XI_U) {
qw_queueMemoryWBRequest2;
+ a_sendDMAAck; // ack count may be zero
l_writeDMADataToMemory;
g_sendInvalidations; // the DMA will collect invalidations
i_popIncomingRequestQueue;
@@ -641,9 +663,10 @@
i_popIncomingRequestQueue;
}
- transition(OI_D, Data, XI_M) {
+ transition(OI_D, Data, XI_U) {
qw_queueMemoryWBRequest;
- l_writeDataToMemory;
+ a_sendDMAAck2; // ack count may be zero
+ p_writeFwdDataToMemory;
l_writeDMADataToMemoryFromTBE;
w_deallocateTBE;
j_popIncomingUnblockQueue;
@@ -821,7 +844,7 @@
q_popMemQueue;
}
- transition({I, S, O, M, IS, SS, OO, MO, MM, MI, MIS, OS, OSS}, Memory_Ack) {
+ transition({I, S, O, M, IS, SS, OO, MO, MM, MI, MIS, OS, OSS, XI_U, XI_M},
Memory_Ack) {
//a_sendAck;
q_popMemQueue;
}
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