changeset cd671122f09c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=cd671122f09c
description:
inorder-alpha-fs: edit inorder model to compile FS mode
diffstat:
10 files changed, 354 insertions(+), 24 deletions(-)
src/cpu/inorder/SConscript | 1
src/cpu/inorder/cpu.cc | 105 +++++++++++++++++++++++++++++---
src/cpu/inorder/cpu.hh | 41 +++++++++++-
src/cpu/inorder/inorder_cpu_builder.cc | 5 +
src/cpu/inorder/inorder_dyn_inst.cc | 28 ++++++++
src/cpu/inorder/inorder_dyn_inst.hh | 16 ++++
src/cpu/inorder/thread_context.cc | 69 +++++++++++++++++----
src/cpu/inorder/thread_context.hh | 40 ++++++++++++
src/cpu/inorder/thread_state.cc | 47 ++++++++++++++
src/cpu/inorder/thread_state.hh | 26 +++++++
diffs (truncated from 668 to 300 lines):
diff -r 8c68656b8564 -r cd671122f09c src/cpu/inorder/SConscript
--- a/src/cpu/inorder/SConscript Mon Sep 14 21:19:40 2009 -0700
+++ b/src/cpu/inorder/SConscript Tue Sep 15 01:44:48 2009 -0400
@@ -79,6 +79,7 @@
Source('resources/mult_div_unit.cc')
Source('resource_pool.cc')
Source('reg_dep_map.cc')
+ Source('thread_state.cc')
Source('thread_context.cc')
Source('cpu.cc')
diff -r 8c68656b8564 -r cd671122f09c src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Mon Sep 14 21:19:40 2009 -0700
+++ b/src/cpu/inorder/cpu.cc Tue Sep 15 01:44:48 2009 -0400
@@ -51,6 +51,15 @@
#include "sim/process.hh"
#include "sim/stat_control.hh"
+#if FULL_SYSTEM
+#include "cpu/quiesce_event.hh"
+#include "sim/system.hh"
+#endif
+
+#if THE_ISA == ALPHA_ISA
+#include "arch/alpha/osfpal.hh"
+#endif
+
using namespace std;
using namespace TheISA;
using namespace ThePipeline;
@@ -171,11 +180,16 @@
timeBuffer(2 , 2),
removeInstsThisCycle(false),
activityRec(params->name, NumStages, 10, params->activity),
+#if FULL_SYSTEM
+ system(params->system),
+ physmem(system->physmem),
+#endif // FULL_SYSTEM
switchCount(0),
deferRegistration(false/*params->deferRegistration*/),
stageTracing(params->stageTracing),
numVirtProcs(1)
{
+ ThreadID active_threads;
cpu_params = params;
resPool = new ResourcePool(this, params);
@@ -183,13 +197,17 @@
// Resize for Multithreading CPUs
thread.resize(numThreads);
- ThreadID active_threads = params->workload.size();
+#if FULL_SYSTEM
+ active_threads = 1;
+#else
+ active_threads = params->workload.size();
if (active_threads > MaxThreads) {
panic("Workload Size too large. Increase the 'MaxThreads'"
"in your InOrder implementation or "
"edit your workload size.");
}
+#endif
// Bind the fetch & data ports from the resource pool.
fetchPortIdx = resPool->getPortIdx(params->fetchMemPort);
@@ -203,6 +221,11 @@
}
for (ThreadID tid = 0; tid < numThreads; ++tid) {
+#if FULL_SYSTEM
+ // SMT is not supported in FS mode yet.
+ assert(this->numThreads == 1);
+ this->thread[tid] = new Thread(this, 0);
+#else
if (tid < (ThreadID)params->workload.size()) {
DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
tid, this->thread[tid]);
@@ -214,6 +237,7 @@
Process* dummy_proc = params->workload[0];
this->thread[tid] = new Thread(this, tid, dummy_proc);
}
+#endif
// Setup the TC that will serve as the interface to the threads/CPU.
InOrderThreadContext *tc = new InOrderThreadContext;
@@ -447,13 +471,6 @@
}
void
-InOrderCPU::readFunctional(Addr addr, uint32_t &buffer)
-{
- tcBase()->getMemPort()->readBlob(addr, (uint8_t*)&buffer,
sizeof(uint32_t));
- buffer = gtoh(buffer);
-}
-
-void
InOrderCPU::reset()
{
for (int i = 0; i < numThreads; i++) {
@@ -468,6 +485,61 @@
return resPool->getPort(if_name, idx);
}
+#if FULL_SYSTEM
+Fault
+InOrderCPU::hwrei(ThreadID tid)
+{
+ panic("hwrei: Unimplemented");
+
+ return NoFault;
+}
+
+
+bool
+InOrderCPU::simPalCheck(int palFunc, ThreadID tid)
+{
+ panic("simPalCheck: Unimplemented");
+
+ return true;
+}
+
+
+Fault
+InOrderCPU::getInterrupts()
+{
+ // Check if there are any outstanding interrupts
+ return this->interrupts->getInterrupt(this->threadContexts[0]);
+}
+
+
+void
+InOrderCPU::processInterrupts(Fault interrupt)
+{
+ // Check for interrupts here. For now can copy the code that
+ // exists within isa_fullsys_traits.hh. Also assume that thread 0
+ // is the one that handles the interrupts.
+ // @todo: Possibly consolidate the interrupt checking code.
+ // @todo: Allow other threads to handle interrupts.
+
+ assert(interrupt != NoFault);
+ this->interrupts->updateIntrInfo(this->threadContexts[0]);
+
+ DPRINTF(InOrderCPU, "Interrupt %s being handled\n", interrupt->name());
+ this->trap(interrupt, 0);
+}
+
+
+void
+InOrderCPU::updateMemPorts()
+{
+ // Update all ThreadContext's memory ports (Functional/Virtual
+ // Ports)
+ ThreadID size = thread.size();
+ for (ThreadID i = 0; i < size; ++i)
+ thread[i]->connectMemPorts(thread[i]->getTC());
+}
+#endif
+
void
InOrderCPU::trap(Fault fault, ThreadID tid, int delay)
{
@@ -1230,6 +1302,22 @@
mainEventQueue.schedule(&tickEvent, curTick);
}
+#if FULL_SYSTEM
+
+void
+InOrderCPU::wakeup()
+{
+ if (this->thread[0]->status() != ThreadContext::Suspended)
+ return;
+
+ this->wakeCPU();
+
+ DPRINTF(Quiesce, "Suspended Processor woken\n");
+ this->threadContexts[0]->activate();
+}
+#endif
+
+#if !FULL_SYSTEM
void
InOrderCPU::syscall(int64_t callnum, ThreadID tid)
{
@@ -1251,6 +1339,7 @@
// Clear Non-Speculative Block Variable
nonSpecInstActive[tid] = false;
}
+#endif
void
InOrderCPU::prefetch(DynInstPtr inst)
diff -r 8c68656b8564 -r cd671122f09c src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hh Mon Sep 14 21:19:40 2009 -0700
+++ b/src/cpu/inorder/cpu.hh Tue Sep 15 01:44:48 2009 -0400
@@ -40,6 +40,7 @@
#include "arch/isa_traits.hh"
#include "arch/types.hh"
+#include "arch/registers.hh"
#include "base/statistics.hh"
#include "base/timebuf.hh"
#include "base/types.hh"
@@ -297,6 +298,32 @@
/** Get a Memory Port */
Port* getPort(const std::string &if_name, int idx = 0);
+#if FULL_SYSTEM
+ /** HW return from error interrupt. */
+ Fault hwrei(ThreadID tid);
+
+ bool simPalCheck(int palFunc, ThreadID tid);
+
+ /** Returns the Fault for any valid interrupt. */
+ Fault getInterrupts();
+
+ /** Processes any an interrupt fault. */
+ void processInterrupts(Fault interrupt);
+
+ /** Halts the CPU. */
+ void halt() { panic("Halt not implemented!\n"); }
+
+ /** Update the Virt and Phys ports of all ThreadContexts to
+ * reflect change in memory connections. */
+ void updateMemPorts();
+
+ /** Check if this address is a valid instruction address. */
+ bool validInstAddr(Addr addr) { return true; }
+
+ /** Check if this address is a valid data address. */
+ bool validDataAddr(Addr addr) { return true; }
+#endif
+
/** trap() - sets up a trap event on the cpuTraps to handle given fault.
* trapCPU() - Traps to handle given fault
*/
@@ -578,8 +605,6 @@
ActivityRecorder activityRec;
public:
- void readFunctional(Addr addr, uint32_t &buffer);
-
/** Number of Active Threads in the CPU */
ThreadID numActiveThreads() { return activeThreads.size(); }
@@ -597,6 +622,10 @@
/** Wakes the CPU, rescheduling the CPU if it's not already active. */
void wakeCPU();
+#if FULL_SYSTEM
+ virtual void wakeup();
+#endif
+
/** Gets a free thread id. Use if thread ids change across system. */
ThreadID getFreeTid();
@@ -622,6 +651,14 @@
return total;
}
+#if FULL_SYSTEM
+ /** Pointer to the system. */
+ System *system;
+
+ /** Pointer to physical memory. */
+ PhysicalMemory *physmem;
+#endif
+
/** The global sequence number counter. */
InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
diff -r 8c68656b8564 -r cd671122f09c src/cpu/inorder/inorder_cpu_builder.cc
--- a/src/cpu/inorder/inorder_cpu_builder.cc Mon Sep 14 21:19:40 2009 -0700
+++ b/src/cpu/inorder/inorder_cpu_builder.cc Tue Sep 15 01:44:48 2009 -0400
@@ -42,12 +42,17 @@
InOrderCPU *
InOrderCPUParams::create()
{
+#if FULL_SYSTEM
+ // Full-system only supports a single thread for the moment.
+ ThreadID actual_num_threads = 1;
+#else
ThreadID actual_num_threads =
(numThreads >= workload.size()) ? numThreads : workload.size();
if (workload.size() == 0) {
fatal("Must specify at least one workload!");
}
+#endif
numThreads = actual_num_threads;
diff -r 8c68656b8564 -r cd671122f09c src/cpu/inorder/inorder_dyn_inst.cc
--- a/src/cpu/inorder/inorder_dyn_inst.cc Mon Sep 14 21:19:40 2009 -0700
+++ b/src/cpu/inorder/inorder_dyn_inst.cc Tue Sep 15 01:44:48 2009 -0400
@@ -297,11 +297,39 @@
return initiateAcc();
}
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