changeset ae3263589c7c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ae3263589c7c
description:
SPARC: Make resTemp in udivcc wide enough to hold all the bits we need.
diffstat:
1 file changed, 2 insertions(+), 1 deletion(-)
src/arch/sparc/isa/decoder.isa | 3 ++-
diffs (13 lines):
diff -r 26b4476e88cd -r ae3263589c7c src/arch/sparc/isa/decoder.isa
--- a/src/arch/sparc/isa/decoder.isa Tue Sep 15 05:30:08 2009 -0700
+++ b/src/arch/sparc/isa/decoder.isa Tue Sep 15 05:48:20 2009 -0700
@@ -226,7 +226,8 @@
if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
else Rd = Rs1.udw / Rs2_or_imm13.udw;}});
0x1E: IntOpCcRes::udivcc({{
- uint32_t resTemp, val2 = Rs2_or_imm13.udw;
+ uint64_t resTemp;
+ uint32_t val2 = Rs2_or_imm13.udw;
int32_t overflow = 0;
if(val2 == 0) fault = new DivisionByZero;
else
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
