This looks pretty obviously correct to me. I'll add it to my patch queue and make sure that it doesn't break anything.
Nate On Mon, Sep 14, 2009 at 10:14 PM, Vince Weaver <vi...@csl.cornell.edu> wrote: > Hello > > the SPARC udivcc instruction was attempting to read bits 63:32 of a > uint32_t, which didn't work very well. > > The below patch changes the value to uint64_t which fixes my test case. > > Vince > > diff -r 3b2d7fdff6b1 src/arch/sparc/isa/decoder.isa > --- a/src/arch/sparc/isa/decoder.isa Fri Sep 11 16:19:31 2009 -0500 > +++ b/src/arch/sparc/isa/decoder.isa Tue Sep 15 01:14:42 2009 -0400 > @@ -226,7 +226,8 @@ > if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero; > else Rd = Rs1.udw / Rs2_or_imm13.udw;}}); > 0x1E: IntOpCcRes::udivcc({{ > - uint32_t resTemp, val2 = Rs2_or_imm13.udw; > + uint64_t resTemp; > + uint32_t val2 = Rs2_or_imm13.udw; > int32_t overflow = 0; > if(val2 == 0) fault = new DivisionByZero; > else > _______________________________________________ > m5-dev mailing list > m5-dev@m5sim.org > http://m5sim.org/mailman/listinfo/m5-dev > > _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev