changeset c248b0348d85 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c248b0348d85
description:
X86: Fix checking the NT bit during an IRET.
diffstat:
1 file changed, 1 insertion(+), 1 deletion(-)
src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
| 2 +-
diffs (12 lines):
diff -r 57fba079b7ff -r c248b0348d85
src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
---
a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
Wed Sep 16 19:28:01 2009 -0700
+++
b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
Wed Sep 16 19:28:30 2009 -0700
@@ -62,7 +62,7 @@
.adjust_env oszIn64Override
# Check for a nested task. This isn't supported at the moment.
- rflag t1, NT
+ rflag t1, 14; #NT bit
panic "Task switching with iret is unimplemented!", flags=(nCEZF,)
#t1 = temp_RIP
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