changeset f4de76601762 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f4de76601762
description:
arch: nuke arch/isa_specific.hh and move stuff to generated
config/the_isa.hh
diffstat:
125 files changed, 208 insertions(+), 163 deletions(-)
SConstruct | 11 ---
src/SConscript | 28 ++++++++--
src/arch/arm/stacktrace.hh | 1
src/arch/isa_specific.hh | 70 -------------------------
src/base/cp_annotate.cc | 1
src/base/cp_annotate.hh | 1
src/base/remote_gdb.cc | 2
src/cpu/base.hh | 1
src/cpu/base_dyn_inst.hh | 1
src/cpu/base_dyn_inst_impl.hh | 7 +-
src/cpu/checker/cpu_impl.hh | 1
src/cpu/checker/thread_context.hh | 1
src/cpu/exetrace.cc | 1
src/cpu/inorder/cpu.cc | 23 ++++----
src/cpu/inorder/cpu.hh | 1
src/cpu/inorder/inorder_dyn_inst.cc | 9 +--
src/cpu/inorder/inorder_dyn_inst.hh | 20 +++----
src/cpu/inorder/inorder_trace.cc | 1
src/cpu/inorder/pipeline_stage.cc | 1
src/cpu/inorder/reg_dep_map.cc | 1
src/cpu/inorder/reg_dep_map.hh | 1
src/cpu/inorder/resources/bpred_unit.cc | 1
src/cpu/inorder/resources/branch_predictor.cc | 1
src/cpu/inorder/resources/cache_unit.cc | 2
src/cpu/inorder/resources/cache_unit.hh | 10 +--
src/cpu/inorder/resources/decode_unit.cc | 1
src/cpu/inorder/resources/fetch_seq_unit.cc | 1
src/cpu/inorder/resources/fetch_seq_unit.hh | 1
src/cpu/inorder/resources/inst_buffer.cc | 2
src/cpu/inorder/resources/inst_buffer_new.cc | 2
src/cpu/inorder/resources/tlb_unit.cc | 2
src/cpu/inorder/resources/tlb_unit.hh | 1
src/cpu/inorder/resources/use_def.cc | 2
src/cpu/inorder/thread_context.cc | 1
src/cpu/inorder/thread_context.hh | 1
src/cpu/inteltrace.cc | 1
src/cpu/legiontrace.cc | 2
src/cpu/o3/bpred_unit_impl.hh | 6 +-
src/cpu/o3/commit_impl.hh | 1
src/cpu/o3/cpu.cc | 2
src/cpu/o3/cpu.hh | 1
src/cpu/o3/decode_impl.hh | 1
src/cpu/o3/dyn_inst.hh | 1
src/cpu/o3/fetch.hh | 1
src/cpu/o3/fetch_impl.hh | 1
src/cpu/o3/free_list.hh | 1
src/cpu/o3/iew_impl.hh | 1
src/cpu/o3/impl.hh | 2
src/cpu/o3/lsq_unit.hh | 1
src/cpu/o3/lsq_unit_impl.hh | 2
src/cpu/o3/regfile.hh | 5 +
src/cpu/o3/rename.hh | 1
src/cpu/o3/rename_impl.hh | 1
src/cpu/o3/rename_map.hh | 3 -
src/cpu/o3/rob.hh | 2
src/cpu/o3/scoreboard.cc | 2
src/cpu/o3/thread_context.hh | 1
src/cpu/o3/thread_context_impl.hh | 1
src/cpu/ozone/cpu.hh | 1
src/cpu/ozone/cpu_impl.hh | 1
src/cpu/ozone/dyn_inst.hh | 1
src/cpu/ozone/dyn_inst_impl.hh | 1
src/cpu/ozone/front_end.hh | 1
src/cpu/ozone/front_end_impl.hh | 4 -
src/cpu/ozone/inorder_back_end_impl.hh | 1
src/cpu/ozone/lsq_unit.hh | 1
src/cpu/ozone/lsq_unit_impl.hh | 1
src/cpu/ozone/lw_back_end_impl.hh | 2
src/cpu/ozone/lw_lsq.hh | 1
src/cpu/ozone/lw_lsq_impl.hh | 4 -
src/cpu/ozone/rename_table.hh | 1
src/cpu/ozone/rename_table_impl.hh | 2
src/cpu/ozone/simple_params.hh | 1
src/cpu/ozone/thread_state.hh | 5 +
src/cpu/profile.hh | 1
src/cpu/simple/atomic.cc | 1
src/cpu/simple/base.cc | 1
src/cpu/simple/base.hh | 1
src/cpu/simple/timing.cc | 1
src/cpu/simple_thread.cc | 1
src/cpu/simple_thread.hh | 1
src/cpu/static_inst.hh | 1
src/cpu/thread_context.cc | 1
src/cpu/thread_context.hh | 1
src/cpu/thread_state.hh | 1
src/dev/alpha/tsunami.cc | 1
src/dev/alpha/tsunami_cchip.cc | 1
src/dev/alpha/tsunami_io.cc | 1
src/dev/alpha/tsunami_pchip.cc | 1
src/dev/baddev.cc | 1
src/dev/ide_disk.cc | 1
src/dev/mips/malta.cc | 2
src/dev/mips/malta_cchip.cc | 3 -
src/dev/mips/malta_io.cc | 1
src/dev/mips/malta_pchip.cc | 1
src/dev/ns_gige.cc | 1
src/dev/platform.cc | 1
src/dev/sinic.cc | 1
src/dev/sparc/dtod.cc | 1
src/dev/sparc/t1000.cc | 1
src/dev/uart8250.cc | 1
src/dev/x86/pc.cc | 1
src/kern/linux/printk.hh | 2
src/kern/system_events.cc | 2
src/kern/tru64/dump_mbuf.cc | 1
src/kern/tru64/tru64.hh | 2
src/kern/tru64/tru64_events.cc | 1
src/mem/cache/builder.cc | 3 -
src/mem/cache/prefetch/base.cc | 4 +
src/mem/packet_access.hh | 1
src/mem/page_table.cc | 1
src/mem/page_table.hh | 1
src/mem/physical.cc | 1
src/mem/port_impl.hh | 3 -
src/mem/rubymem.cc | 1
src/mem/translating_port.cc | 2
src/mem/vport.cc | 1
src/sim/arguments.cc | 7 +-
src/sim/process.cc | 2
src/sim/process.hh | 8 +-
src/sim/pseudo_inst.cc | 4 -
src/sim/syscall_emul.cc | 2
src/sim/syscall_emul.hh | 1
src/sim/system.cc | 3 +
src/sim/system.hh | 8 +-
diffs (truncated from 1779 to 300 lines):
diff -r ef5fae93a3b2 -r f4de76601762 SConstruct
--- a/SConstruct Tue Sep 22 18:12:39 2009 -0700
+++ b/SConstruct Wed Sep 23 08:34:21 2009 -0700
@@ -742,17 +742,10 @@
# list of ISAs from env['ALL_ISA_LIST'].
def gen_switch_hdr(target, source, env):
fname = str(target[0])
- bname = basename(fname)
f = open(fname, 'w')
- f.write('#include "arch/isa_specific.hh"\n')
- cond = '#if'
- for isa in all_isa_list:
- f.write('%s THE_ISA == %s_ISA\n#include "%s/%s/%s"\n'
- % (cond, isa.upper(), dname, isa, bname))
- cond = '#elif'
- f.write('#else\n#error "THE_ISA not set"\n#endif\n')
+ isa = env['TARGET_ISA'].lower()
+ print >>f, '#include "%s/%s/%s"' % (dname, isa, basename(fname))
f.close()
- return 0
# String to print when generating header
def gen_switch_hdr_string(target, source, env):
diff -r ef5fae93a3b2 -r f4de76601762 src/SConscript
--- a/src/SConscript Tue Sep 22 18:12:39 2009 -0700
+++ b/src/SConscript Wed Sep 23 08:34:21 2009 -0700
@@ -228,9 +228,6 @@
for extra_dir in extras_dir_list:
env.Append(CPPPATH=Dir(extra_dir))
-# Add a flag defining what THE_ISA should be for all compilation
-env.Append(CPPDEFINES=[('THE_ISA','%s_ISA' % env['TARGET_ISA'].upper())])
-
# Workaround for bug in SCons version > 0.97d20071212
# Scons bug id: 2006 M5 Bug id: 308
for root, dirs, files in os.walk(base_dir, topdown=True):
@@ -261,6 +258,31 @@
for opt in export_vars:
env.ConfigFile(opt)
+def makeTheISA(source, target, env):
+ f = file(str(target[0]), 'w')
+
+ isas = [ src.get_contents() for src in source ]
+ target = env['TARGET_ISA']
+ def define(isa):
+ return isa.upper() + '_ISA'
+
+ def namespace(isa):
+ return isa[0].upper() + isa[1:].lower() + 'ISA'
+
+
+ print >>f, '#ifndef __CONFIG_THE_ISA_HH__'
+ print >>f, '#define __CONFIG_THE_ISA_HH__'
+ print >>f
+ for i,isa in enumerate(isas):
+ print >>f, '#define %s %d' % (define(isa), i + 1)
+ print >>f
+ print >>f, '#define THE_ISA %s' % (define(target))
+ print >>f, '#define TheISA %s' % (namespace(target))
+ print >>f
+ print >>f, '#endif // __CONFIG_THE_ISA_HH__'
+
+env.Command('config/the_isa.hh', map(Value, all_isa_list), makeTheISA)
+
########################################################################
#
# Prevent any SimObjects from being added after this point, they
diff -r ef5fae93a3b2 -r f4de76601762 src/arch/arm/stacktrace.hh
--- a/src/arch/arm/stacktrace.hh Tue Sep 22 18:12:39 2009 -0700
+++ b/src/arch/arm/stacktrace.hh Wed Sep 23 08:34:21 2009 -0700
@@ -34,6 +34,7 @@
#define __ARCH_ARM_STACKTRACE_HH__
#include "base/trace.hh"
+#include "config/the_isa.hh"
#include "cpu/static_inst.hh"
class ThreadContext;
diff -r ef5fae93a3b2 -r f4de76601762 src/arch/isa_specific.hh
--- a/src/arch/isa_specific.hh Tue Sep 22 18:12:39 2009 -0700
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,70 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#ifndef __ARCH_ISA_SPECIFIC_HH__
-#define __ARCH_ISA_SPECIFIC_HH__
-
-//This file provides a mechanism for other source code to bring in
-//files from the ISA being compiled in.
-
-//These are constants so you can selectively compile code based on the isa.
-//To use them, do something like:
-//
-//#if THE_ISA == YOUR_FAVORITE_ISA
-// conditional_code
-//#endif
-//
-//Note that this is how this file sets up the TheISA macro.
-
-//These macros have numerical values because otherwise the preprocessor
-//would treat them as 0 in comparisons.
-#define ALPHA_ISA 21064
-#define SPARC_ISA 42
-#define MIPS_ISA 34000
-#define X86_ISA 8086
-#define ARM_ISA 6
-
-//These tell the preprocessor where to find the files of a particular
-//ISA, and set the "TheISA" macro for use elsewhere.
-#if THE_ISA == ALPHA_ISA
- #define TheISA AlphaISA
-#elif THE_ISA == SPARC_ISA
- #define TheISA SparcISA
-#elif THE_ISA == MIPS_ISA
- #define TheISA MipsISA
-#elif THE_ISA == X86_ISA
- #define TheISA X86ISA
-#elif THE_ISA == ARM_ISA
- #define TheISA ArmISA
-#else
- #error "THE_ISA not set"
-#endif
-
-#endif
diff -r ef5fae93a3b2 -r f4de76601762 src/base/cp_annotate.cc
--- a/src/base/cp_annotate.cc Tue Sep 22 18:12:39 2009 -0700
+++ b/src/base/cp_annotate.cc Wed Sep 23 08:34:21 2009 -0700
@@ -35,6 +35,7 @@
#include "base/loader/object_file.hh"
#include "base/output.hh"
#include "base/trace.hh"
+#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
#include "sim/arguments.hh"
#include "sim/core.hh"
diff -r ef5fae93a3b2 -r f4de76601762 src/base/cp_annotate.hh
--- a/src/base/cp_annotate.hh Tue Sep 22 18:12:39 2009 -0700
+++ b/src/base/cp_annotate.hh Wed Sep 23 08:34:21 2009 -0700
@@ -41,6 +41,7 @@
#include "base/trace.hh"
#include "base/types.hh"
#include "config/cp_annotate.hh"
+#include "config/the_isa.hh"
#include "sim/serialize.hh"
#include "sim/startup.hh"
#include "sim/system.hh"
diff -r ef5fae93a3b2 -r f4de76601762 src/base/remote_gdb.cc
--- a/src/base/remote_gdb.cc Tue Sep 22 18:12:39 2009 -0700
+++ b/src/base/remote_gdb.cc Wed Sep 23 08:34:21 2009 -0700
@@ -131,9 +131,9 @@
#include "base/remote_gdb.hh"
#include "base/socket.hh"
#include "base/trace.hh"
+#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
#include "cpu/static_inst.hh"
-//#include "mem/physical.hh"
#include "mem/port.hh"
#include "mem/translating_port.hh"
#include "sim/system.hh"
diff -r ef5fae93a3b2 -r f4de76601762 src/cpu/base.hh
--- a/src/cpu/base.hh Tue Sep 22 18:12:39 2009 -0700
+++ b/src/cpu/base.hh Wed Sep 23 08:34:21 2009 -0700
@@ -38,6 +38,7 @@
#include "arch/microcode_rom.hh"
#include "base/statistics.hh"
#include "config/full_system.hh"
+#include "config/the_isa.hh"
#include "sim/eventq.hh"
#include "sim/insttracer.hh"
#include "mem/mem_object.hh"
diff -r ef5fae93a3b2 -r f4de76601762 src/cpu/base_dyn_inst.hh
--- a/src/cpu/base_dyn_inst.hh Tue Sep 22 18:12:39 2009 -0700
+++ b/src/cpu/base_dyn_inst.hh Wed Sep 23 08:34:21 2009 -0700
@@ -39,6 +39,7 @@
#include "base/fast_alloc.hh"
#include "base/trace.hh"
#include "config/full_system.hh"
+#include "config/the_isa.hh"
#include "cpu/o3/comm.hh"
#include "cpu/exetrace.hh"
#include "cpu/inst_seq.hh"
diff -r ef5fae93a3b2 -r f4de76601762 src/cpu/base_dyn_inst_impl.hh
--- a/src/cpu/base_dyn_inst_impl.hh Tue Sep 22 18:12:39 2009 -0700
+++ b/src/cpu/base_dyn_inst_impl.hh Wed Sep 23 08:34:21 2009 -0700
@@ -35,12 +35,11 @@
#include "base/cprintf.hh"
#include "base/trace.hh"
-
-#include "sim/faults.hh"
+#include "config/the_isa.hh"
+#include "cpu/base_dyn_inst.hh"
#include "cpu/exetrace.hh"
#include "mem/request.hh"
-
-#include "cpu/base_dyn_inst.hh"
+#include "sim/faults.hh"
#define NOHASH
#ifndef NOHASH
diff -r ef5fae93a3b2 -r f4de76601762 src/cpu/checker/cpu_impl.hh
--- a/src/cpu/checker/cpu_impl.hh Tue Sep 22 18:12:39 2009 -0700
+++ b/src/cpu/checker/cpu_impl.hh Wed Sep 23 08:34:21 2009 -0700
@@ -32,6 +32,7 @@
#include <string>
#include "base/refcnt.hh"
+#include "config/the_isa.hh"
#include "cpu/base_dyn_inst.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/simple_thread.hh"
diff -r ef5fae93a3b2 -r f4de76601762 src/cpu/checker/thread_context.hh
--- a/src/cpu/checker/thread_context.hh Tue Sep 22 18:12:39 2009 -0700
+++ b/src/cpu/checker/thread_context.hh Wed Sep 23 08:34:21 2009 -0700
@@ -32,6 +32,7 @@
#define __CPU_CHECKER_THREAD_CONTEXT_HH__
#include "arch/types.hh"
+#include "config/the_isa.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
diff -r ef5fae93a3b2 -r f4de76601762 src/cpu/exetrace.cc
--- a/src/cpu/exetrace.cc Tue Sep 22 18:12:39 2009 -0700
+++ b/src/cpu/exetrace.cc Wed Sep 23 08:34:21 2009 -0700
@@ -38,6 +38,7 @@
#include "cpu/exetrace.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
+#include "config/the_isa.hh"
#include "enums/OpClass.hh"
using namespace std;
diff -r ef5fae93a3b2 -r f4de76601762 src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Tue Sep 22 18:12:39 2009 -0700
+++ b/src/cpu/inorder/cpu.cc Wed Sep 23 08:34:21 2009 -0700
@@ -33,21 +33,22 @@
#include "arch/utility.hh"
#include "config/full_system.hh"
+#include "config/the_isa.hh"
+#include "cpu/activity.hh"
+#include "cpu/base.hh"
#include "cpu/exetrace.hh"
-#include "cpu/activity.hh"
+#include "cpu/inorder/cpu.hh"
+#include "cpu/inorder/first_stage.hh"
+#include "cpu/inorder/inorder_dyn_inst.hh"
+#include "cpu/inorder/pipeline_traits.hh"
+#include "cpu/inorder/resource_pool.hh"
+#include "cpu/inorder/resources/resource_list.hh"
+#include "cpu/inorder/thread_context.hh"
+#include "cpu/inorder/thread_state.hh"
#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
-#include "cpu/base.hh"
-#include "cpu/inorder/inorder_dyn_inst.hh"
-#include "cpu/inorder/thread_context.hh"
-#include "cpu/inorder/thread_state.hh"
-#include "cpu/inorder/cpu.hh"
+#include "mem/translating_port.hh"
#include "params/InOrderCPU.hh"
-#include "cpu/inorder/pipeline_traits.hh"
-#include "cpu/inorder/first_stage.hh"
-#include "cpu/inorder/resources/resource_list.hh"
-#include "cpu/inorder/resource_pool.hh"
-#include "mem/translating_port.hh"
#include "sim/process.hh"
#include "sim/stat_control.hh"
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