You need to add RUBY=True to the scons command line
On Thu, Sep 24, 2009 at 9:41 AM, Korey Sewell <[email protected]> wrote: > So I didnt get the ruby updates... > > Is there a command line option to add that into the build? > > On Thu, Sep 24, 2009 at 12:31 PM, Korey Sewell <[email protected]> wrote: >> >> changeset 8dc0b1a04a96 in /z/repo/m5 >> details: http://repo.m5sim.org/m5?cmd=changeset;node=8dc0b1a04a96 >> description: >> mips-stats: update regressions of arguments fix >> >> diffstat: >> >> 11 files changed, 429 insertions(+), 429 deletions(-) >> tests/quick/00.hello/ref/mips/linux/inorder-timing/simout | 8 >> tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt | 210 ++-- >> tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini | 2 >> tests/quick/00.hello/ref/mips/linux/o3-timing/simout | 10 >> tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt | 424 >> +++++----- >> tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini | 2 >> tests/quick/00.hello/ref/mips/linux/simple-atomic/simout | 10 >> tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt | 16 >> tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini | 2 >> tests/quick/00.hello/ref/mips/linux/simple-timing/simout | 10 >> tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt | 164 +-- >> >> diffs (truncated from 1376 to 300 lines): >> >> diff -r 9bc3e4611009 -r 8dc0b1a04a96 >> tests/quick/00.hello/ref/mips/linux/inorder-timing/simout >> --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout Wed Sep 23 >> 18:28:29 2009 -0700 >> +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout Thu Sep 24 >> 12:30:53 2009 -0400 >> @@ -5,13 +5,13 @@ >> All Rights Reserved >> >> >> -M5 compiled May 13 2009 01:40:41 >> -M5 revision 4c418376e894 6202 default tip >> -M5 started May 13 2009 01:40:42 >> +M5 compiled Sep 24 2009 12:19:09 >> +M5 revision 9bc3e4611009+ 6661+ default tip >> +M5 started Sep 24 2009 12:19:46 >> M5 executing on zooks >> command line: build/MIPS_SE/m5.fast -d >> build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re >> tests/run.py >> build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing >> Global frequency set at 1000000000000 ticks per second >> info: Entering event queue @ 0. Starting simulation... >> info: Increasing stack size by one page. >> Hello World! >> -Exiting @ tick 29437500 because target called exit() >> +Exiting @ tick 29521500 because target called exit() >> diff -r 9bc3e4611009 -r 8dc0b1a04a96 >> tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt >> --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt >> Wed Sep 23 18:28:29 2009 -0700 >> +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt >> Thu Sep 24 12:30:53 2009 -0400 >> @@ -1,44 +1,44 @@ >> >> ---------- Begin Simulation Statistics ---------- >> -host_inst_rate 23976 >> # Simulator instruction rate (inst/s) >> -host_mem_usage 152688 >> # Number of bytes of host memory used >> -host_seconds 0.24 >> # Real time elapsed on the host >> -host_tick_rate 124659634 >> # Simulator tick rate (ticks/s) >> +host_inst_rate 29581 >> # Simulator instruction rate (inst/s) >> +host_mem_usage 155804 >> # Number of bytes of host memory used >> +host_seconds 0.19 >> # Real time elapsed on the host >> +host_tick_rate 153369596 >> # Simulator tick rate (ticks/s) >> sim_freq 1000000000000 >> # Frequency of simulated ticks >> -sim_insts 5656 >> # Number of instructions simulated >> -sim_seconds 0.000029 >> # Number of seconds simulated >> -sim_ticks 29437500 >> # Number of ticks simulated >> -system.cpu.AGEN-Unit.instReqsProcessed 2055 >> # Number of Instructions Requests that completed in this resource. >> -system.cpu.Branch-Predictor.instReqsProcessed 5657 >> # Number of Instructions Requests that completed in this resource. >> -system.cpu.Branch-Predictor.predictedNotTaken 783 >> # Number of Branches Predicted As Not Taken (False). >> +sim_insts 5685 >> # Number of instructions simulated >> +sim_seconds 0.000030 >> # Number of seconds simulated >> +sim_ticks 29521500 >> # Number of ticks simulated >> +system.cpu.AGEN-Unit.instReqsProcessed 2058 >> # Number of Instructions Requests that completed in this resource. >> +system.cpu.Branch-Predictor.instReqsProcessed 5686 >> # Number of Instructions Requests that completed in this resource. >> +system.cpu.Branch-Predictor.predictedNotTaken 789 >> # Number of Branches Predicted As Not Taken (False). >> system.cpu.Branch-Predictor.predictedTaken 96 >> # Number of Branches Predicted As Taken (True). >> -system.cpu.Decode-Unit.instReqsProcessed 5657 >> # Number of Instructions Requests that completed in this resource. >> -system.cpu.Execution-Unit.instReqsProcessed 3598 >> # Number of Instructions Requests that completed in this resource. >> -system.cpu.Execution-Unit.predictedNotTakenIncorrect 515 >> # Number of Branches Incorrectly Predicted As Not Taken). >> +system.cpu.Decode-Unit.instReqsProcessed 5686 >> # Number of Instructions Requests that completed in this resource. >> +system.cpu.Execution-Unit.instReqsProcessed 3624 >> # Number of Instructions Requests that completed in this resource. >> +system.cpu.Execution-Unit.predictedNotTakenIncorrect 516 >> # Number of Branches Incorrectly Predicted As Not Taken). >> system.cpu.Execution-Unit.predictedTakenIncorrect 34 >> # Number of Branches Incorrectly Predicted As Taken. >> system.cpu.Fetch-Buffer-T0.instReqsProcessed 0 >> # Number of Instructions Requests that completed in this resource. >> system.cpu.Fetch-Buffer-T0.instsBypassed 0 >> # Number of Instructions Bypassed. >> system.cpu.Fetch-Buffer-T1.instReqsProcessed 0 >> # Number of Instructions Requests that completed in this resource. >> system.cpu.Fetch-Buffer-T1.instsBypassed 0 >> # Number of Instructions Bypassed. >> -system.cpu.Fetch-Seq-Unit.instReqsProcessed 11315 >> # Number of Instructions Requests that completed in this resource. >> -system.cpu.Graduation-Unit.instReqsProcessed 5656 >> # Number of Instructions Requests that completed in this resource. >> +system.cpu.Fetch-Seq-Unit.instReqsProcessed 11373 >> # Number of Instructions Requests that completed in this resource. >> +system.cpu.Graduation-Unit.instReqsProcessed 5685 >> # Number of Instructions Requests that completed in this resource. >> system.cpu.Mult-Div-Unit.divInstReqsProcessed 1 >> # Number of Divide Requests Processed. >> system.cpu.Mult-Div-Unit.instReqsProcessed 8 >> # Number of Instructions Requests that completed in this resource. >> system.cpu.Mult-Div-Unit.multInstReqsProcessed 3 >> # Number of Multiply Requests Processed. >> -system.cpu.RegFile-Manager.instReqsProcessed 10420 >> # Number of Instructions Requests that completed in this resource. >> -system.cpu.committedInsts 5656 >> # Number of Instructions Simulated (Per-Thread) >> -system.cpu.committedInsts_total 5656 >> # Number of Instructions Simulated (Total) >> -system.cpu.cpi 10.409477 >> # CPI: Cycles Per Instruction (Per-Thread) >> -system.cpu.cpi_total 10.409477 >> # CPI: Total CPI of All Threads >> -system.cpu.dcache.ReadReq_accesses 1131 >> # number of ReadReq accesses(hits+misses) >> +system.cpu.RegFile-Manager.instReqsProcessed 10479 >> # Number of Instructions Requests that completed in this resource. >> +system.cpu.committedInsts 5685 >> # Number of Instructions Simulated (Per-Thread) >> +system.cpu.committedInsts_total 5685 >> # Number of Instructions Simulated (Total) >> +system.cpu.cpi 10.385928 >> # CPI: Cycles Per Instruction (Per-Thread) >> +system.cpu.cpi_total 10.385928 >> # CPI: Total CPI of All Threads >> +system.cpu.dcache.ReadReq_accesses 1134 >> # number of ReadReq accesses(hits+misses) >> system.cpu.dcache.ReadReq_avg_miss_latency 56207.317073 >> # average ReadReq miss latency >> system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53207.317073 >> # average ReadReq mshr miss latency >> -system.cpu.dcache.ReadReq_hits 1049 >> # number of ReadReq hits >> +system.cpu.dcache.ReadReq_hits 1052 >> # number of ReadReq hits >> system.cpu.dcache.ReadReq_miss_latency 4609000 >> # number of ReadReq miss cycles >> -system.cpu.dcache.ReadReq_miss_rate 0.072502 >> # miss rate for ReadReq accesses >> +system.cpu.dcache.ReadReq_miss_rate 0.072310 >> # miss rate for ReadReq accesses >> system.cpu.dcache.ReadReq_misses 82 >> # number of ReadReq misses >> system.cpu.dcache.ReadReq_mshr_miss_latency 4363000 >> # number of ReadReq MSHR miss cycles >> -system.cpu.dcache.ReadReq_mshr_miss_rate 0.072502 >> # mshr miss rate for ReadReq accesses >> +system.cpu.dcache.ReadReq_mshr_miss_rate 0.072310 >> # mshr miss rate for ReadReq accesses >> system.cpu.dcache.ReadReq_mshr_misses 82 >> # number of ReadReq MSHR misses >> system.cpu.dcache.WriteReq_accesses 924 >> # number of WriteReq accesses(hits+misses) >> system.cpu.dcache.WriteReq_avg_miss_latency 56554.687500 >> # average WriteReq miss latency >> @@ -52,48 +52,48 @@ >> system.cpu.dcache.WriteReq_mshr_misses 64 >> # number of WriteReq MSHR misses >> system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value >> # average number of cycles each access was blocked >> system.cpu.dcache.avg_blocked_cycles::no_targets no_value >> # average number of cycles each access was blocked >> -system.cpu.dcache.avg_refs 14.568182 >> # Average number of references to valid blocks. >> +system.cpu.dcache.avg_refs 14.590909 >> # Average number of references to valid blocks. >> system.cpu.dcache.blocked::no_mshrs 0 >> # number of cycles access was blocked >> system.cpu.dcache.blocked::no_targets 0 >> # number of cycles access was blocked >> system.cpu.dcache.blocked_cycles::no_mshrs 0 >> # number of cycles access was blocked >> system.cpu.dcache.blocked_cycles::no_targets 0 >> # number of cycles access was blocked >> system.cpu.dcache.cache_copies 0 >> # number of cache copies performed >> -system.cpu.dcache.demand_accesses 2055 >> # number of demand (read+write) accesses >> +system.cpu.dcache.demand_accesses 2058 >> # number of demand (read+write) accesses >> system.cpu.dcache.demand_avg_miss_latency 56359.589041 >> # average overall miss latency >> system.cpu.dcache.demand_avg_mshr_miss_latency 53359.589041 >> # average overall mshr miss latency >> -system.cpu.dcache.demand_hits 1909 >> # number of demand (read+write) hits >> +system.cpu.dcache.demand_hits 1912 >> # number of demand (read+write) hits >> system.cpu.dcache.demand_miss_latency 8228500 >> # number of demand (read+write) miss cycles >> -system.cpu.dcache.demand_miss_rate 0.071046 >> # miss rate for demand accesses >> +system.cpu.dcache.demand_miss_rate 0.070943 >> # miss rate for demand accesses >> system.cpu.dcache.demand_misses 146 >> # number of demand (read+write) misses >> system.cpu.dcache.demand_mshr_hits 0 >> # number of demand (read+write) MSHR hits >> system.cpu.dcache.demand_mshr_miss_latency 7790500 >> # number of demand (read+write) MSHR miss cycles >> -system.cpu.dcache.demand_mshr_miss_rate 0.071046 >> # mshr miss rate for demand accesses >> +system.cpu.dcache.demand_mshr_miss_rate 0.070943 >> # mshr miss rate for demand accesses >> system.cpu.dcache.demand_mshr_misses 146 >> # number of demand (read+write) MSHR misses >> system.cpu.dcache.fast_writes 0 >> # number of fast writes performed >> system.cpu.dcache.mshr_cap_events 0 >> # number of times MSHR cap was activated >> system.cpu.dcache.no_allocate_misses 0 >> # Number of misses that were no-allocate >> -system.cpu.dcache.overall_accesses 2055 >> # number of overall (read+write) accesses >> +system.cpu.dcache.overall_accesses 2058 >> # number of overall (read+write) accesses >> system.cpu.dcache.overall_avg_miss_latency 56359.589041 >> # average overall miss latency >> system.cpu.dcache.overall_avg_mshr_miss_latency 53359.589041 >> # average overall mshr miss latency >> system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value >> # average overall mshr uncacheable latency >> -system.cpu.dcache.overall_hits 1909 >> # number of overall hits >> +system.cpu.dcache.overall_hits 1912 >> # number of overall hits >> system.cpu.dcache.overall_miss_latency 8228500 >> # number of overall miss cycles >> -system.cpu.dcache.overall_miss_rate 0.071046 >> # miss rate for overall accesses >> +system.cpu.dcache.overall_miss_rate 0.070943 >> # miss rate for overall accesses >> system.cpu.dcache.overall_misses 146 >> # number of overall misses >> system.cpu.dcache.overall_mshr_hits 0 >> # number of overall MSHR hits >> system.cpu.dcache.overall_mshr_miss_latency 7790500 >> # number of overall MSHR miss cycles >> -system.cpu.dcache.overall_mshr_miss_rate 0.071046 >> # mshr miss rate for overall accesses >> +system.cpu.dcache.overall_mshr_miss_rate 0.070943 >> # mshr miss rate for overall accesses >> system.cpu.dcache.overall_mshr_misses 146 >> # number of overall MSHR misses >> system.cpu.dcache.overall_mshr_uncacheable_latency 0 >> # number of overall MSHR uncacheable cycles >> system.cpu.dcache.overall_mshr_uncacheable_misses 0 >> # number of overall MSHR uncacheable misses >> system.cpu.dcache.replacements 0 >> # number of replacements >> system.cpu.dcache.sampled_refs 132 >> # Sample count of references to valid blocks. >> system.cpu.dcache.soft_prefetch_mshr_full 0 >> # number of mshr full events for SW prefetching instrutions >> -system.cpu.dcache.tagsinuse 84.205216 >> # Cycle average of tags in use >> -system.cpu.dcache.total_refs 1923 >> # Total number of references to valid blocks. >> +system.cpu.dcache.tagsinuse 84.209307 >> # Cycle average of tags in use >> +system.cpu.dcache.total_refs 1926 >> # Total number of references to valid blocks. >> system.cpu.dcache.warmup_cycle 0 >> # Cycle when the warmup percentage was hit. >> system.cpu.dcache.writebacks 0 >> # number of writebacks >> -system.cpu.dcache_port.instReqsProcessed 2054 >> # Number of Instructions Requests that completed in this resource. >> +system.cpu.dcache_port.instReqsProcessed 2057 >> # Number of Instructions Requests that completed in this resource. >> system.cpu.dtb.accesses 0 >> # DTB accesses >> system.cpu.dtb.hits 0 >> # DTB hits >> system.cpu.dtb.misses 0 >> # DTB misses >> @@ -103,62 +103,62 @@ >> system.cpu.dtb.write_accesses 0 >> # DTB write accesses >> system.cpu.dtb.write_hits 0 >> # DTB write hits >> system.cpu.dtb.write_misses 0 >> # DTB write misses >> -system.cpu.icache.ReadReq_accesses 5658 >> # number of ReadReq accesses(hits+misses) >> -system.cpu.icache.ReadReq_avg_miss_latency 55772.277228 >> # average ReadReq miss latency >> -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52772.277228 >> # average ReadReq mshr miss latency >> -system.cpu.icache.ReadReq_hits 5355 >> # number of ReadReq hits >> -system.cpu.icache.ReadReq_miss_latency 16899000 >> # number of ReadReq miss cycles >> -system.cpu.icache.ReadReq_miss_rate 0.053552 >> # miss rate for ReadReq accesses >> -system.cpu.icache.ReadReq_misses 303 >> # number of ReadReq misses >> -system.cpu.icache.ReadReq_mshr_miss_latency 15990000 >> # number of ReadReq MSHR miss cycles >> -system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 >> # mshr miss rate for ReadReq accesses >> -system.cpu.icache.ReadReq_mshr_misses 303 >> # number of ReadReq MSHR misses >> +system.cpu.icache.ReadReq_accesses 5687 >> # number of ReadReq accesses(hits+misses) >> +system.cpu.icache.ReadReq_avg_miss_latency 55773.026316 >> # average ReadReq miss latency >> +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52773.026316 >> # average ReadReq mshr miss latency >> +system.cpu.icache.ReadReq_hits 5383 >> # number of ReadReq hits >> +system.cpu.icache.ReadReq_miss_latency 16955000 >> # number of ReadReq miss cycles >> +system.cpu.icache.ReadReq_miss_rate 0.053455 >> # miss rate for ReadReq accesses >> +system.cpu.icache.ReadReq_misses 304 >> # number of ReadReq misses >> +system.cpu.icache.ReadReq_mshr_miss_latency 16043000 >> # number of ReadReq MSHR miss cycles >> +system.cpu.icache.ReadReq_mshr_miss_rate 0.053455 >> # mshr miss rate for ReadReq accesses >> +system.cpu.icache.ReadReq_mshr_misses 304 >> # number of ReadReq MSHR misses >> system.cpu.icache.avg_blocked_cycles::no_mshrs no_value >> # average number of cycles each access was blocked >> system.cpu.icache.avg_blocked_cycles::no_targets no_value >> # average number of cycles each access was blocked >> -system.cpu.icache.avg_refs 17.673267 >> # Average number of references to valid blocks. >> +system.cpu.icache.avg_refs 17.707237 >> # Average number of references to valid blocks. >> system.cpu.icache.blocked::no_mshrs 0 >> # number of cycles access was blocked >> system.cpu.icache.blocked::no_targets 0 >> # number of cycles access was blocked >> system.cpu.icache.blocked_cycles::no_mshrs 0 >> # number of cycles access was blocked >> system.cpu.icache.blocked_cycles::no_targets 0 >> # number of cycles access was blocked >> system.cpu.icache.cache_copies 0 >> # number of cache copies performed >> -system.cpu.icache.demand_accesses 5658 >> # number of demand (read+write) accesses >> -system.cpu.icache.demand_avg_miss_latency 55772.277228 >> # average overall miss latency >> -system.cpu.icache.demand_avg_mshr_miss_latency 52772.277228 >> # average overall mshr miss latency >> -system.cpu.icache.demand_hits 5355 >> # number of demand (read+write) hits >> -system.cpu.icache.demand_miss_latency 16899000 >> # number of demand (read+write) miss cycles >> -system.cpu.icache.demand_miss_rate 0.053552 >> # miss rate for demand accesses >> -system.cpu.icache.demand_misses 303 >> # number of demand (read+write) misses >> +system.cpu.icache.demand_accesses 5687 >> # number of demand (read+write) accesses >> +system.cpu.icache.demand_avg_miss_latency 55773.026316 >> # average overall miss latency >> +system.cpu.icache.demand_avg_mshr_miss_latency 52773.026316 >> # average overall mshr miss latency >> +system.cpu.icache.demand_hits 5383 >> # number of demand (read+write) hits >> +system.cpu.icache.demand_miss_latency 16955000 >> # number of demand (read+write) miss cycles >> +system.cpu.icache.demand_miss_rate 0.053455 >> # miss rate for demand accesses >> +system.cpu.icache.demand_misses 304 >> # number of demand (read+write) misses >> system.cpu.icache.demand_mshr_hits 0 >> # number of demand (read+write) MSHR hits >> -system.cpu.icache.demand_mshr_miss_latency 15990000 >> # number of demand (read+write) MSHR miss cycles >> -system.cpu.icache.demand_mshr_miss_rate 0.053552 >> # mshr miss rate for demand accesses >> -system.cpu.icache.demand_mshr_misses 303 >> # number of demand (read+write) MSHR misses >> +system.cpu.icache.demand_mshr_miss_latency 16043000 >> # number of demand (read+write) MSHR miss cycles >> +system.cpu.icache.demand_mshr_miss_rate 0.053455 >> # mshr miss rate for demand accesses >> +system.cpu.icache.demand_mshr_misses 304 >> # number of demand (read+write) MSHR misses >> system.cpu.icache.fast_writes 0 >> # number of fast writes performed >> system.cpu.icache.mshr_cap_events 0 >> # number of times MSHR cap was activated >> system.cpu.icache.no_allocate_misses 0 >> # Number of misses that were no-allocate >> -system.cpu.icache.overall_accesses 5658 >> # number of overall (read+write) accesses >> -system.cpu.icache.overall_avg_miss_latency 55772.277228 >> # average overall miss latency >> -system.cpu.icache.overall_avg_mshr_miss_latency 52772.277228 >> # average overall mshr miss latency >> +system.cpu.icache.overall_accesses 5687 >> # number of overall (read+write) accesses >> +system.cpu.icache.overall_avg_miss_latency 55773.026316 >> # average overall miss latency >> +system.cpu.icache.overall_avg_mshr_miss_latency 52773.026316 >> # average overall mshr miss latency >> system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value >> # average overall mshr uncacheable latency >> -system.cpu.icache.overall_hits 5355 >> # number of overall hits >> -system.cpu.icache.overall_miss_latency 16899000 >> # number of overall miss cycles >> -system.cpu.icache.overall_miss_rate 0.053552 >> # miss rate for overall accesses >> -system.cpu.icache.overall_misses 303 >> # number of overall misses >> +system.cpu.icache.overall_hits 5383 >> # number of overall hits >> +system.cpu.icache.overall_miss_latency 16955000 >> # number of overall miss cycles >> +system.cpu.icache.overall_miss_rate 0.053455 >> # miss rate for overall accesses >> +system.cpu.icache.overall_misses 304 >> # number of overall misses >> system.cpu.icache.overall_mshr_hits 0 >> # number of overall MSHR hits >> -system.cpu.icache.overall_mshr_miss_latency 15990000 >> # number of overall MSHR miss cycles >> -system.cpu.icache.overall_mshr_miss_rate 0.053552 >> # mshr miss rate for overall accesses >> -system.cpu.icache.overall_mshr_misses 303 >> # number of overall MSHR misses >> +system.cpu.icache.overall_mshr_miss_latency 16043000 >> # number of overall MSHR miss cycles >> +system.cpu.icache.overall_mshr_miss_rate 0.053455 >> # mshr miss rate for overall accesses >> +system.cpu.icache.overall_mshr_misses 304 >> # number of overall MSHR misses >> system.cpu.icache.overall_mshr_uncacheable_latency 0 >> # number of overall MSHR uncacheable cycles >> system.cpu.icache.overall_mshr_uncacheable_misses 0 >> # number of overall MSHR uncacheable misses >> system.cpu.icache.replacements 13 >> # number of replacements >> -system.cpu.icache.sampled_refs 303 >> # Sample count of references to valid blocks. >> +system.cpu.icache.sampled_refs 304 >> # Sample count of references to valid blocks. >> system.cpu.icache.soft_prefetch_mshr_full 0 >> # number of mshr full events for SW prefetching instrutions >> -system.cpu.icache.tagsinuse 135.958324 >> # Cycle average of tags in use >> -system.cpu.icache.total_refs 5355 >> # Total number of references to valid blocks. >> +system.cpu.icache.tagsinuse 136.385131 >> # Cycle average of tags in use >> +system.cpu.icache.total_refs 5383 >> # Total number of references to valid blocks. >> system.cpu.icache.warmup_cycle 0 >> # Cycle when the warmup percentage was hit. >> system.cpu.icache.writebacks 0 >> # number of writebacks >> -system.cpu.icache_port.instReqsProcessed 5657 >> # Number of Instructions Requests that completed in this resource. >> -system.cpu.ipc 0.096066 >> # IPC: Instructions Per Cycle (Per-Thread) >> -system.cpu.ipc_total 0.096066 >> # IPC: Total IPC of All Threads >> +system.cpu.icache_port.instReqsProcessed 5686 >> # Number of Instructions Requests that completed in this resource. >> +system.cpu.ipc 0.096284 >> # IPC: Instructions Per Cycle (Per-Thread) >> +system.cpu.ipc_total 0.096284 >> # IPC: Total IPC of All Threads >> system.cpu.itb.accesses 0 >> # DTB accesses >> system.cpu.itb.hits 0 >> # DTB hits >> system.cpu.itb.misses 0 >> # DTB misses >> @@ -177,16 +177,16 @@ >> system.cpu.l2cache.ReadExReq_mshr_miss_latency 2004000 >> # number of ReadExReq MSHR miss cycles >> system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 >> # mshr miss rate for ReadExReq accesses >> system.cpu.l2cache.ReadExReq_mshr_misses 50 >> # number of ReadExReq MSHR misses >> -system.cpu.l2cache.ReadReq_accesses 385 >> # number of ReadReq accesses(hits+misses) >> -system.cpu.l2cache.ReadReq_avg_miss_latency 52052.219321 >> # average ReadReq miss latency >> -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40026.109661 >> # average ReadReq mshr miss latency >> +system.cpu.l2cache.ReadReq_accesses 386 >> # number of ReadReq accesses(hits+misses) >> +system.cpu.l2cache.ReadReq_avg_miss_latency 52052.083333 >> # average ReadReq miss latency >> +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40026.041667 >> # average ReadReq mshr miss latency >> system.cpu.l2cache.ReadReq_hits 2 >> # number of ReadReq hits >> -system.cpu.l2cache.ReadReq_miss_latency 19936000 >> # number of ReadReq miss cycles >> -system.cpu.l2cache.ReadReq_miss_rate 0.994805 >> # miss rate for ReadReq accesses >> -system.cpu.l2cache.ReadReq_misses 383 >> # number of ReadReq misses >> -system.cpu.l2cache.ReadReq_mshr_miss_latency 15330000 >> # number of ReadReq MSHR miss cycles >> -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994805 >> # mshr miss rate for ReadReq accesses >> -system.cpu.l2cache.ReadReq_mshr_misses 383 >> # number of ReadReq MSHR misses >> +system.cpu.l2cache.ReadReq_miss_latency 19988000 >> # number of ReadReq miss cycles >> +system.cpu.l2cache.ReadReq_miss_rate 0.994819 >> # miss rate for ReadReq accesses >> +system.cpu.l2cache.ReadReq_misses 384 >> # number of ReadReq misses >> +system.cpu.l2cache.ReadReq_mshr_miss_latency 15370000 >> # number of ReadReq MSHR miss cycles >> +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994819 >> # mshr miss rate for ReadReq accesses >> +system.cpu.l2cache.ReadReq_mshr_misses 384 >> # number of ReadReq MSHR misses >> system.cpu.l2cache.UpgradeReq_accesses 14 >> # number of UpgradeReq accesses(hits+misses) >> system.cpu.l2cache.UpgradeReq_avg_miss_latency 52535.714286 >> # average UpgradeReq miss latency >> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40071.428571 >> # average UpgradeReq mshr miss latency >> @@ -198,53 +198,53 @@ >> system.cpu.l2cache.UpgradeReq_mshr_misses 14 >> # number of UpgradeReq MSHR misses >> system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value >> # average number of cycles each access was blocked >> system.cpu.l2cache.avg_blocked_cycles::no_targets no_value >> # average number of cycles each access was blocked >> -system.cpu.l2cache.avg_refs 0.005420 >> # Average number of references to valid blocks. >> +system.cpu.l2cache.avg_refs 0.005405 >> # Average number of references to valid blocks. >> system.cpu.l2cache.blocked::no_mshrs 0 >> # number of cycles access was blocked >> system.cpu.l2cache.blocked::no_targets 0 >> # number of cycles access was blocked >> system.cpu.l2cache.blocked_cycles::no_mshrs 0 >> # number of cycles access was blocked >> system.cpu.l2cache.blocked_cycles::no_targets 0 >> # number of cycles access was blocked >> system.cpu.l2cache.cache_copies 0 >> # number of cache copies performed >> -system.cpu.l2cache.demand_accesses 435 >> # number of demand (read+write) accesses >> -system.cpu.l2cache.demand_avg_miss_latency 52103.926097 >> # average overall miss latency >> -system.cpu.l2cache.demand_avg_mshr_miss_latency 40032.332564 >> # average overall mshr miss latency >> +system.cpu.l2cache.demand_accesses 436 >> # number of demand (read+write) accesses >> +system.cpu.l2cache.demand_avg_miss_latency 52103.686636 >> # average overall miss latency >> +system.cpu.l2cache.demand_avg_mshr_miss_latency 40032.258065 >> # average overall mshr miss latency >> system.cpu.l2cache.demand_hits 2 >> # number of demand (read+write) hits >> -system.cpu.l2cache.demand_miss_latency 22561000 >> # number of demand (read+write) miss cycles >> -system.cpu.l2cache.demand_miss_rate 0.995402 >> # miss rate for demand accesses >> _______________________________________________ >> m5-dev mailing list >> [email protected] >> http://m5sim.org/mailman/listinfo/m5-dev > > > > -- > - Korey > > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
