changeset 8b5bc1a777bc in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8b5bc1a777bc
description:
O3: Add flag to control whether faulting instructions are traced.
When enabled, faulting instructions appear in the trace twice
(once when they fault and again when they're re-executed).
This flag is set by the Exec compound flag for backwards compatibility.
diffstat:
2 files changed, 8 insertions(+), 5 deletions(-)
src/cpu/SConscript | 5 +++--
src/cpu/o3/commit_impl.hh | 8 +++++---
diffs (38 lines):
diff -r 3199397fd905 -r 8b5bc1a777bc src/cpu/SConscript
--- a/src/cpu/SConscript Sat Sep 26 10:50:50 2009 -0700
+++ b/src/cpu/SConscript Sat Sep 26 10:50:50 2009 -0700
@@ -160,6 +160,7 @@
TraceFlag('ExecEnable')
TraceFlag('ExecCPSeq')
TraceFlag('ExecEffAddr')
+TraceFlag('ExecFaulting', 'Trace faulting instructions')
TraceFlag('ExecFetchSeq')
TraceFlag('ExecOpClass')
TraceFlag('ExecRegDelta')
@@ -176,6 +177,6 @@
TraceFlag('Quiesce')
CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
- 'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro' ])
+ 'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting' ])
CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
- 'ExecEffAddr', 'ExecResult', 'ExecMicro' ])
+ 'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting' ])
diff -r 3199397fd905 -r 8b5bc1a777bc src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh Sat Sep 26 10:50:50 2009 -0700
+++ b/src/cpu/o3/commit_impl.hh Sat Sep 26 10:50:50 2009 -0700
@@ -1076,9 +1076,11 @@
commitStatus[tid] = TrapPending;
if (head_inst->traceData) {
- head_inst->traceData->setFetchSeq(head_inst->seqNum);
- head_inst->traceData->setCPSeq(thread[tid]->numInst);
- head_inst->traceData->dump();
+ if (DTRACE(ExecFaulting)) {
+ head_inst->traceData->setFetchSeq(head_inst->seqNum);
+ head_inst->traceData->setCPSeq(thread[tid]->numInst);
+ head_inst->traceData->dump();
+ }
delete head_inst->traceData;
head_inst->traceData = NULL;
}
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
