I agree about the variable latencies for L1 caches, but the concern is just that I wasnt sure if this is what's intended considering the original example pre-changeset 4444 was set to a 1 cycle latency whereas now you'll get by default 2. I figured the former was the desired behavior was then 1 cycle and we may have slightly fooled a user or 2 then if they were expecting that 1 cycle to still hold...
Now I do realize this is just an example so if people cared they should create their own config file or change it for themselves in the se.py if it's a results critical parameter, so no biggie if everyone is OK with that... On Fri, Oct 2, 2009 at 10:26 PM, Steve Reinhardt <[email protected]> wrote: > Hi Korey, > > I'm not quite sure what your concern is here... if it's just that the > L1 cache latency is multiple cycles, that's not at all unusual on > high-performance processors. > > Steve > > On Fri, Oct 2, 2009 at 6:52 PM, Korey Sewell <[email protected]> wrote: > > Hey all, > > there may be a subtle flaw in how we configure CPUs and Caches in our > > example configuration (se.py/Caches.py). > > > > By default, the CPU is set to 2 GHz => 500 ps per tick. > > By default, the BaseCache latency is set to 1ns => 1000ps. > > > > So what happens is, if you have a cache hit on tick X (0) you are not > > getting your data on tick X+1 (500), you are getting it on X+2 (1000). > > > > Excuse me if I'm just overlooking the obvious, but am I calculating > > something wrong here? > > > > Looks like in changeset 4444, we went from giving a scalar cycle latency > > (i.e. 1) for Caches to a set period to wait (i.e. 1ns). But again, since > the > > CPU is ticking every 500ps and the Cache is responding on hits every > 1000ps > > I dont think we got the desired behavior at least in the case I'm > > considering.... > > > > Thoughts anyone? > > > > -- > > - Korey > > > > _______________________________________________ > > m5-dev mailing list > > [email protected] > > http://m5sim.org/mailman/listinfo/m5-dev > > > > > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > -- - Korey
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