Hi all, So now I've posted my PowerPC ISA patches, I'm trying to get it all working with O3CPU :-). I've come up against a difficulty right away. The processor is deadlocked because a branch instruction at the head of the ROB isn't marked as ready to execute. This is because it depends on a miscreg. When I look at the code, I can't see where this should be sorted out. In inst_queue_impl.hh in wakeDependents, we have the following comment before the code that skips over dependents on miscregs:
// Special case of uniq or control registers. They are not // handled by the IQ and thus have no dependency graph entry. // @todo Figure out a cleaner way to handle this. My question is this: since they are not handled by the IQ, where are the miscreg dependents woken? I can't find this anywhere in the code. Can someone point me to the place it happens? In PowerPC, a lot of branches depend on a miscreg (the control register, possibly also the count register) so this could be a problem for me. Thanks Tim -- The University of Edinburgh is a charitable body, registered in Scotland, with registration number SC005336. _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
