# HG changeset patch
# User Timothy M. Jones <[email protected]>
# Date 1255617066 -3600
# Node ID f5adc197dc663e55ac4cc3125f97d636884e4183
# Parent 3ea509cf8f00ef6f3804093516340d425de5eaa4
Fix floating point condition register calculation.
Adds support for 64 bit floats (i.e. doubles) and fixes a small bug
in the computation of the condition result.
diff --git a/src/arch/powerpc/insts/floating.hh
b/src/arch/powerpc/insts/floating.hh
--- a/src/arch/powerpc/insts/floating.hh
+++ b/src/arch/powerpc/insts/floating.hh
@@ -62,6 +62,12 @@
}
inline bool
+ isNan(uint64_t val_bits) const
+ {
+ return ((bits(val_bits, 62, 52) == 0x7FF) && bits(val_bits, 51, 0));
+ }
+
+ inline bool
isNan(float val) const
{
void *val_ptr = &val;
@@ -69,6 +75,14 @@
return isNan(val_bits);
}
+ inline bool
+ isNan(double val) const
+ {
+ void *val_ptr = &val;
+ uint64_t val_bits = *(uint64_t *) val_ptr;
+ return isNan(val_bits);
+ }
+
// Test for SNaN (NaN with high order bit of fraction set to 0)
inline bool
isSnan(uint32_t val_bits) const
@@ -121,11 +135,11 @@
// Compute the CR field
inline uint32_t
- makeCRField(float a, float b) const
+ makeCRField(double a, double b) const
{
uint32_t c = 0;
if (isNan(a) || isNan(b)) { c = 0x1; }
- if (a < b) { c = 0x8; }
+ else if (a < b) { c = 0x8; }
else if (a > b) { c = 0x4; }
else { c = 0x2; }
return c;
--
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