On Wed, 21 Oct 2009 22:14:43 +0100, Steve Reinhardt <[email protected]> wrote:
>> I believe that unaligned data accesses may be fairly common. There is no >> restriction on their use. At the very least they are causing failures in >> several benchmarks. If I were to implement a similar thing in O3 would >> this be the best way to do it? I.e. should it be one store causing two >> requests, or split into two stores each with one request? >> > > The ISA should issue a single read() or write() call, which the CPU model > should split into at most two requests, guaranteeing only that they do > not > cross a cache-block boundary. Basically just what the SimpleCPU models > are > already doing, though I can understand if that wasn't perfectly obvious > from > reading the code :-). > Ok, great, thanks Steve. In that case I'll base the changes to O3 on the SimpleCPU models. I think I'm fairly clear about what it's doing, now that I've read it over a couple of times. Cheers Tim -- The University of Edinburgh is a charitable body, registered in Scotland, with registration number SC005336. _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
