Make the TLB translation timing instead of atomic for BaseDynInst. diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -45,6 +45,7 @@ #include "cpu/inst_seq.hh" #include "cpu/op_class.hh" #include "cpu/static_inst.hh" +#include "cpu/translation.hh" #include "mem/packet.hh" #include "sim/system.hh" #include "sim/tlb.hh" @@ -129,6 +130,10 @@ Fault write(T data, Addr addr, unsigned flags, uint64_t *res); + template + void finishTranslation(Fault translate_fault, RequestPtr &req, T &data, + uint64_t *res, bool read); + void prefetch(Addr addr, unsigned flags); void writeHint(Addr addr, int size, unsigned flags); Fault copySrcTranslate(Addr src); @@ -861,38 +866,9 @@ Request *req = new Request(asid, addr, sizeof(T), flags, this->PC, thread->contextId(), threadNumber); - fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Read); - - if (req->isUncacheable()) - isUncacheable = true; - - if (fault == NoFault) { - effAddr = req->getVaddr(); - effAddrValid = true; - physEffAddr = req->getPaddr(); - memReqFlags = req->getFlags(); - -#if 0 - if (cpu->system->memctrl->badaddr(physEffAddr)) { - fault = TheISA::genMachineCheckFault(); - data = (T)-1; - this->setExecuted(); - } else { - fault = cpu->read(req, data, lqIdx); - } -#else - fault = cpu->read(req, data, lqIdx); -#endif - } else { - // Return a fixed value to keep simulation deterministic even - // along misspeculated paths. - data = (T)-1; - - // Commit will have to clean up whatever happened. Set this - // instruction as executed. - this->setExecuted(); - delete req; - } + DataTranslation *trans = + new DataTranslation(this, data, NULL, BaseTLB::Read); + cpu->dtb->translateTiming(req, thread->getTC(), trans, BaseTLB::Read); if (traceData) { traceData->setAddr(addr); @@ -916,8 +892,20 @@ Request *req = new Request(asid, addr, sizeof(T), flags, this->PC, thread->contextId(), threadNumber); - fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write); + DataTranslation *trans = + new DataTranslation(this, data, res, BaseTLB::Write); + cpu->dtb->translateTiming(req, thread->getTC(), trans, BaseTLB::Write); + return fault; +} + +template +template +inline void +BaseDynInst::finishTranslation(Fault translate_fault, RequestPtr &req, + T &data, uint64_t *res, bool read) +{ + fault = translate_fault; if (req->isUncacheable()) isUncacheable = true; @@ -931,20 +919,25 @@ assert(res); req->setExtraData(*res); } -#if 0 - if (cpu->system->memctrl->badaddr(physEffAddr)) { - fault = TheISA::genMachineCheckFault(); + + if (read) { + fault = cpu->read(req, data, lqIdx); } else { fault = cpu->write(req, data, sqIdx); } -#else - fault = cpu->write(req, data, sqIdx); -#endif } else { + if (read) { + + // Return a fixed value to keep simulation deterministic even + // along misspeculated paths. + data = (T)-1; + + // Commit will have to clean up whatever happened. Set this + // instruction as executed. + this->setExecuted(); + } delete req; } - - return fault; } #endif // __CPU_BASE_DYN_INST_HH__ diff --git a/src/cpu/translation.hh b/src/cpu/translation.hh new file mode 100644 --- /dev/null +++ b/src/cpu/translation.hh @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2002-2005 The Regents of The University of Michigan + * Copyright (c) 2009 The University of Edinburgh + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Steve Reinhardt + * Timothy M. Jones + */ + +#ifndef __CPU_TRANSLATION_HH__ +#define __CPU_TRANSLATION_HH__ + +#include "sim/tlb.hh" + +// Forward declaration +template +class BaseDynInst; + +template +class DataTranslation : public BaseTLB::Translation +{ + protected: + typedef BaseDynInst DynInst; + typedef RefCountingPtr DynInstPtr; + + DynInstPtr inst; + T data; + uint64_t *res; + BaseTLB::Mode mode; + + public: + DataTranslation(DynInstPtr _inst, T _data, uint64_t *_res, + BaseTLB::Mode _mode) + : inst(_inst), data(_data), res(_res), mode(_mode) + { + assert(mode == BaseTLB::Read || mode == BaseTLB::Write); + } + + void + finish(Fault fault, RequestPtr req, ThreadContext *tc, + BaseTLB::Mode mode) + { + assert(mode == this->mode); + inst->finishTranslation(fault, req, data, res, mode == BaseTLB::Read); + delete this; + } +}; + +#endif // __CPU_TRANSLATION_HH__