On Mon, 26 Oct 2009, Vince Weaver wrote: > I managed to get together code that could handle shifts of 0-7 bytes, but > couldn't figure out a way to handle 8-15 properly without some sort of > conditional branch.
One thing I just thought of (for the psrldq_VRo_Ib code). The Ib field is a constant immediate, right? So would it be possible to just have 16 different uop sequences generated, one for each shift amount? Inefficient, but it would avoid trying to code it up in a general way. I'm not sure if the current uop generation code can handle splitting up an instruction like that though. And thinking about it more, there's actually maybe only 4 different cases, not 16. Hmmm. Vince _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
