changeset 2a131d15ec34 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=2a131d15ec34
description:
ARM: Implement the shadow registers using register flattening.
diffstat:
1 file changed, 41 insertions(+), 2 deletions(-)
src/arch/arm/isa.hh | 43 +++++++++++++++++++++++++++++++++++++++++--
diffs (74 lines):
diff -r 07546255fb03 -r 2a131d15ec34 src/arch/arm/isa.hh
--- a/src/arch/arm/isa.hh Sun Nov 08 00:07:35 2009 -0800
+++ b/src/arch/arm/isa.hh Sun Nov 08 00:07:49 2009 -0800
@@ -44,14 +44,44 @@
{
protected:
MiscReg miscRegs[NumMiscRegs];
+ const IntRegIndex *intRegMap;
+
+ void
+ updateRegMap(CPSR cpsr)
+ {
+ switch (cpsr.mode) {
+ case MODE_USER:
+ case MODE_SYSTEM:
+ intRegMap = IntRegUsrMap;
+ break;
+ case MODE_FIQ:
+ intRegMap = IntRegFiqMap;
+ break;
+ case MODE_IRQ:
+ intRegMap = IntRegIrqMap;
+ break;
+ case MODE_SVC:
+ intRegMap = IntRegSvcMap;
+ break;
+ case MODE_ABORT:
+ intRegMap = IntRegAbtMap;
+ break;
+ case MODE_UNDEFINED:
+ intRegMap = IntRegUndMap;
+ break;
+ default:
+ panic("Unrecognized mode setting in CPSR.\n");
+ }
+ }
public:
void clear()
{
memset(miscRegs, 0, sizeof(miscRegs));
CPSR cpsr = 0;
- cpsr.mode = MODE_USER;
+ cpsr.mode = MODE_SYSTEM;
miscRegs[MISCREG_CPSR] = cpsr;
+ updateRegMap(cpsr);
//XXX We need to initialize the rest of the state.
}
@@ -79,6 +109,9 @@
void
setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
{
+ if (misc_reg == MISCREG_CPSR) {
+ updateRegMap(val);
+ }
assert(misc_reg < NumMiscRegs);
miscRegs[misc_reg] = val;
}
@@ -86,7 +119,13 @@
int
flattenIntIndex(int reg)
{
- return reg;
+ assert(reg >= 0);
+ if (reg < NUM_ARCH_INTREGS) {
+ return intRegMap[reg];
+ } else {
+ assert(reg < NUM_INTREGS);
+ return reg;
+ }
}
int
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