changeset ea7c71a3433a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ea7c71a3433a
description:
ARM: Add in more bits for the mon mode.
diffstat:
3 files changed, 5 insertions(+)
src/arch/arm/isa.hh | 3 +++
src/arch/arm/miscregs.hh | 1 +
src/arch/arm/types.hh | 1 +
diffs (35 lines):
diff -r 93f1e520447d -r ea7c71a3433a src/arch/arm/isa.hh
--- a/src/arch/arm/isa.hh Sun Nov 08 02:00:55 2009 -0800
+++ b/src/arch/arm/isa.hh Sun Nov 08 02:01:02 2009 -0800
@@ -63,6 +63,9 @@
case MODE_SVC:
intRegMap = IntRegSvcMap;
break;
+ case MODE_MON:
+ intRegMap = IntRegMonMap;
+ break;
case MODE_ABORT:
intRegMap = IntRegAbtMap;
break;
diff -r 93f1e520447d -r ea7c71a3433a src/arch/arm/miscregs.hh
--- a/src/arch/arm/miscregs.hh Sun Nov 08 02:00:55 2009 -0800
+++ b/src/arch/arm/miscregs.hh Sun Nov 08 02:01:02 2009 -0800
@@ -59,6 +59,7 @@
MISCREG_SPSR_FIQ,
MISCREG_SPSR_IRQ,
MISCREG_SPSR_SVC,
+ MISCREG_SPSR_MON,
MISCREG_SPSR_UND,
MISCREG_SPSR_ABT,
MISCREG_FPSR,
diff -r 93f1e520447d -r ea7c71a3433a src/arch/arm/types.hh
--- a/src/arch/arm/types.hh Sun Nov 08 02:00:55 2009 -0800
+++ b/src/arch/arm/types.hh Sun Nov 08 02:01:02 2009 -0800
@@ -156,6 +156,7 @@
MODE_FIQ = 17,
MODE_IRQ = 18,
MODE_SVC = 19,
+ MODE_MON = 22,
MODE_ABORT = 23,
MODE_UNDEFINED = 27,
MODE_SYSTEM = 31
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