changeset a5322e816a2a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a5322e816a2a
description:
ARM: Support forcing load/store multiple to use user registers.
diffstat:
4 files changed, 32 insertions(+), 26 deletions(-)
src/arch/arm/insts/macromem.hh | 25 ++++++-------------------
src/arch/arm/intregs.hh | 7 +++++++
src/arch/arm/isa.hh | 5 ++++-
src/arch/arm/isa/formats/macromem.isa | 21 +++++++++++++++------
diffs (141 lines):
diff -r c469a9365a4a -r a5322e816a2a src/arch/arm/insts/macromem.hh
--- a/src/arch/arm/insts/macromem.hh Sun Nov 08 15:16:59 2009 -0800
+++ b/src/arch/arm/insts/macromem.hh Sun Nov 08 15:49:03 2009 -0800
@@ -84,33 +84,20 @@
*/
class ArmMacroMemoryOp : public PredMacroOp
{
- protected:
+ protected:
/// Memory request flags. See mem_req_base.hh.
unsigned memAccessFlags;
uint32_t reglist;
uint32_t ones;
- uint32_t puswl,
- prepost,
- up,
- psruser,
- writeback,
- loadop;
ArmMacroMemoryOp(const char *mnem, ExtMachInst _machInst,
OpClass __opClass)
- : PredMacroOp(mnem, _machInst, __opClass),
- memAccessFlags(0),
- reglist(machInst.regList), ones(0),
- puswl(machInst.puswl),
- prepost(machInst.puswl.prepost),
- up(machInst.puswl.up),
- psruser(machInst.puswl.psruser),
- writeback(machInst.puswl.writeback),
- loadop(machInst.puswl.loadOp)
+ : PredMacroOp(mnem, _machInst, __opClass), memAccessFlags(0),
+ reglist(machInst.regList), ones(0)
{
ones = number_of_ones(reglist);
- numMicroops = ones + writeback + 1;
+ numMicroops = ones + machInst.puswl.writeback + 1;
// Remember that writeback adds a uop
microOps = new StaticInstPtr[numMicroops];
}
@@ -121,7 +108,7 @@
*/
class ArmMacroFPAOp : public PredMacroOp
{
- protected:
+ protected:
uint32_t puswl,
prepost,
up,
@@ -150,7 +137,7 @@
*/
class ArmMacroFMOp : public PredMacroOp
{
- protected:
+ protected:
uint32_t punwl,
prepost,
up,
diff -r c469a9365a4a -r a5322e816a2a src/arch/arm/intregs.hh
--- a/src/arch/arm/intregs.hh Sun Nov 08 15:16:59 2009 -0800
+++ b/src/arch/arm/intregs.hh Sun Nov 08 15:49:03 2009 -0800
@@ -324,6 +324,13 @@
return IntRegFiqMap[index];
}
+static inline IntRegIndex
+intRegForceUser(unsigned index)
+{
+ assert(index < NUM_ARCH_INTREGS);
+ return (IntRegIndex)(index + NUM_INTREGS);
+}
+
}
#endif
diff -r c469a9365a4a -r a5322e816a2a src/arch/arm/isa.hh
--- a/src/arch/arm/isa.hh Sun Nov 08 15:16:59 2009 -0800
+++ b/src/arch/arm/isa.hh Sun Nov 08 15:49:03 2009 -0800
@@ -125,8 +125,11 @@
assert(reg >= 0);
if (reg < NUM_ARCH_INTREGS) {
return intRegMap[reg];
+ } else if (reg < NUM_INTREGS) {
+ return reg;
} else {
- assert(reg < NUM_INTREGS);
+ reg -= NUM_INTREGS;
+ assert(reg < NUM_ARCH_INTREGS);
return reg;
}
}
diff -r c469a9365a4a -r a5322e816a2a src/arch/arm/isa/formats/macromem.isa
--- a/src/arch/arm/isa/formats/macromem.isa Sun Nov 08 15:16:59 2009 -0800
+++ b/src/arch/arm/isa/formats/macromem.isa Sun Nov 08 15:49:03 2009 -0800
@@ -180,11 +180,12 @@
%(constructor)s;
uint32_t regs = reglist;
uint32_t addr = 0;
+ bool up = machInst.puswl.up;
if (!up)
addr = (ones << 2) - 4;
- if (prepost)
+ if (machInst.puswl.prepost)
addr += 4;
// Add 0 to Rn and stick it in ureg0.
@@ -198,10 +199,18 @@
reg++;
replaceBits(regs, reg, 0);
- if (loadop)
- microOps[i] = new MicroLdrUop(machInst, reg, INTREG_UREG0, addr);
- else
- microOps[i] = new MicroStrUop(machInst, reg, INTREG_UREG0, addr);
+ unsigned regIdx = reg;
+ if (machInst.puswl.psruser) {
+ regIdx = intRegForceUser(regIdx);
+ }
+
+ if (machInst.puswl.loadOp) {
+ microOps[i] =
+ new MicroLdrUop(machInst, regIdx, INTREG_UREG0, addr);
+ } else {
+ microOps[i] =
+ new MicroStrUop(machInst, regIdx, INTREG_UREG0, addr);
+ }
if (up)
addr += 4;
@@ -210,7 +219,7 @@
}
StaticInstPtr &lastUop = microOps[numMicroops - 1];
- if (writeback) {
+ if (machInst.puswl.writeback) {
if (up) {
lastUop = new MicroAddiUop(machInst, RN, RN, ones * 4);
} else {
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