Ok, that all makes sense. I didn't realize that it was squashed. Nate
On Mon, Nov 9, 2009 at 2:03 PM, Gabriel Michael Black <[email protected]> wrote: > Are you referring to the PageFault in the SE only code in the TLB? It's > really just a signal to the CPU that the translation failed. If the > translation failure was silent, the CPU might still try to do the access and > cause more trouble. Once the fault makes it into the CPU, it gets squashed > and life moves on. Even so, the page fault is appropriate because that's > what happened, the process didn't have that address in its page table. > > Gabe > > Quoting nathan binkert <[email protected]>: > >> Do we really want to page fault on a prefetch? I can see a TLB fill, >> but a fault? (or are these wrapped into one thing?) >> >> Nate >> _______________________________________________ >> m5-dev mailing list >> [email protected] >> http://m5sim.org/mailman/listinfo/m5-dev >> > > > > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
