-----Original Message----- From: [email protected] [mailto:[email protected]] Sent: Monday, November 09, 2009 10:33 AM To: Beckmann, Brad Subject: [PATCH 25 of 31] ruby: cache configuration fix to use bytes
# HG changeset patch # User Brad Beckmann <[email protected]> # Date 1257791383 28800 # Node ID 88d149d9aa74962334d4f7ef5c669c0c35585e29 # Parent 0fc897a4b97ff79237df2edf240e4e438adc5de7 ruby: cache configuration fix to use bytes Changed cache size to be in bytes instead of kb so that testers can use very small caches and increase the chance of writeback races. diff -r 0fc897a4b97f -r 88d149d9aa74 src/mem/ruby/config/MI_example-homogeneous.rb --- a/src/mem/ruby/config/MI_example-homogeneous.rb Mon Nov 09 10:29:43 2009 -0800 +++ b/src/mem/ruby/config/MI_example-homogeneous.rb Mon Nov 09 10:29:43 2009 -0800 @@ -13,7 +13,7 @@ # default values num_cores = 2 -l1_cache_size_kb = 32 +l1_cache_size_kb = 32768 l1_cache_assoc = 8 l1_cache_latency = 1 num_memories = 2 @@ -37,6 +37,12 @@ elsif $*[i] == "-s" memory_size_mb = $*[i+1].to_i i = i + 1 + elsif $*[i] == "-C" + l1_cache_size_bytes = $*[i+1].to_i + i = i + 1 + elsif $*[i] == "-A" + l1_cache_assoc = $*[i+1].to_i + i = i + 1 elsif $*[i] == "-D" num_dma = $*[i+1].to_i i = i + 1 @@ -51,7 +57,7 @@ require protocol+".rb" num_cores.times { |n| - cache = SetAssociativeCache.new("l1u_"+n.to_s, l1_cache_size_kb, l1_cache_latency, l1_cache_assoc, "PSEUDO_LRU") + cache = SetAssociativeCache.new("l1u_"+n.to_s, l1_cache_size_bytes, l1_cache_latency, l1_cache_assoc, "PSEUDO_LRU") sequencer = Sequencer.new("Sequencer_"+n.to_s, cache, cache) iface_ports << sequencer net_ports << MI_example_CacheController.new("L1CacheController_"+n.to_s, diff -r 0fc897a4b97f -r 88d149d9aa74 src/mem/ruby/config/cfg.rb --- a/src/mem/ruby/config/cfg.rb Mon Nov 09 10:29:43 2009 -0800 +++ b/src/mem/ruby/config/cfg.rb Mon Nov 09 10:29:43 2009 -0800 @@ -401,17 +401,17 @@ end class Cache < LibRubyObject - attr :size_kb, :latency + attr :size, :latency attr_writer :controller - def initialize(obj_name, size_kb, latency) + def initialize(obj_name, size, latency) super(obj_name) - assert size_kb.is_a?(Integer), "Cache size must be an integer" - @size_kb = size_kb + assert size.is_a?(Integer), "Cache size must be an integer" + @size = size @latency = latency end def args - "controller "[email protected]_name+" size_kb "+...@size_kb.to_s+" latency "[email protected]_s + "controller "[email protected]_name+" size "[email protected]_s+" latency "[email protected]_s end end @@ -422,8 +422,8 @@ # when an integer, it represents the number of cycles for a hit # when a float, it represents the cache access time in ns # when set to "auto", libruby will attempt to find a realistic latency by running CACTI - def initialize(obj_name, size_kb, latency, assoc, replacement_policy) - super(obj_name, size_kb, latency) + def initialize(obj_name, size, latency, assoc, replacement_policy) + super(obj_name, size, latency) @assoc = assoc @replacement_policy = replacement_policy end @@ -431,7 +431,7 @@ def calculateLatency() if @latency == "auto" cacti_args = Array.new() - cacti_args << (@size_kb*1024) << RubySystem.block_size_bytes << @assoc + cacti_args << (@size) << RubySystem.block_size_bytes << @assoc cacti_args << 1 << 0 << 0 << 0 << 1 cacti_args << RubySystem.tech_nm << RubySystem.block_size_bytes*8 cacti_args << 0 << 0 << 0 << 1 << 0 << 0 << 0 << 0 << 1 diff -r 0fc897a4b97f -r 88d149d9aa74 src/mem/ruby/system/CacheMemory.cc --- a/src/mem/ruby/system/CacheMemory.cc Mon Nov 09 10:29:43 2009 -0800 +++ b/src/mem/ruby/system/CacheMemory.cc Mon Nov 09 10:29:43 2009 -0800 @@ -52,12 +52,12 @@ void CacheMemory::init(const vector<string> & argv) { - int cache_size = 0; + int cache_size = -1; string policy; m_controller = NULL; for (uint32 i=0; i<argv.size(); i+=2) { - if (argv[i] == "size_kb") { + if (argv[i] == "size") { cache_size = atoi(argv[i+1].c_str()); } else if (argv[i] == "latency") { m_latency = atoi(argv[i+1].c_str()); @@ -72,8 +72,12 @@ } } + assert(cache_size != -1); + m_cache_num_sets = cache_size / m_cache_assoc; + assert(m_cache_num_sets > 1); m_cache_num_set_bits = log_int(m_cache_num_sets); + assert(m_cache_num_set_bits > 0); if(policy == "PSEUDO_LRU") m_replacementPolicy_ptr = new PseudoLRUPolicy(m_cache_num_sets, m_cache_assoc); _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
