changeset 7d2767d7896f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7d2767d7896f
description:
ARM: More accurately describe the effects of using the control operands.
diffstat:
1 file changed, 6 insertions(+), 6 deletions(-)
src/arch/arm/isa/operands.isa | 12 ++++++------
diffs (22 lines):
diff -r cdc62b81747e -r 7d2767d7896f src/arch/arm/isa/operands.isa
--- a/src/arch/arm/isa/operands.isa Sat Nov 14 19:22:29 2009 -0800
+++ b/src/arch/arm/isa/operands.isa Sat Nov 14 19:22:29 2009 -0800
@@ -81,12 +81,12 @@
#Memory Operand
'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30),
- 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 40),
- 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', 'IsInteger', 41),
- 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 42),
- 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', 'IsInteger', 43),
- 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', 'IsInteger', 44),
- 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', 'IsInteger', 45),
+ 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'),
40),
+ 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', (None, None, 'IsControl'),
41),
+ 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', (None, None, 'IsControl'),
42),
+ 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', (None, None, 'IsControl'),
43),
+ 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', (None, None, 'IsControl'),
44),
+ 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', (None, None, 'IsControl'),
45),
'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 50),
'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 51)
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