changeset ad8698d92176 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ad8698d92176
description:
ARM: Fix up the implmentation of the mrs instruction.
diffstat:
1 file changed, 4 insertions(+), 2 deletions(-)
src/arch/arm/isa/decoder.isa | 6 ++++--
diffs (23 lines):
diff -r 7d2767d7896f -r ad8698d92176 src/arch/arm/isa/decoder.isa
--- a/src/arch/arm/isa/decoder.isa Sat Nov 14 19:22:29 2009 -0800
+++ b/src/arch/arm/isa/decoder.isa Sat Nov 14 19:22:29 2009 -0800
@@ -110,7 +110,9 @@
}
1: decode MISC_OPCODE {
0x0: decode OPCODE {
- 0x8: PredOp::mrs_cpsr({{ Rd = Cpsr | CondCodes; }});
+ 0x8: PredOp::mrs_cpsr({{
+ Rd = (Cpsr | CondCodes) & 0xF8FF03DF;
+ }});
0x9: PredOp::msr_cpsr({{
//assert(!RN<1:0>);
if (OPCODE_18) {
@@ -120,7 +122,7 @@
CondCodes = mbits(Rm, 31,27);
}
}});
- 0xa: PredOp::mrs_spsr({{ Rd = 0; // should be SPSR}});
+ 0xa: PredOp::mrs_spsr({{ Rd = Spsr; }});
0xb: WarnUnimpl::msr_spsr();
}
0x1: decode OPCODE {
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