changeset c2b6531c305c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c2b6531c305c
description:
ARM: Check in the actual change from the last commit.
The last commit was somehow empty. This was what was supposed to go in
it.
diffstat:
1 file changed, 12 insertions(+), 12 deletions(-)
src/arch/arm/isa/decoder.isa | 24 ++++++++++++------------
diffs (47 lines):
diff -r 097d0a64650f -r c2b6531c305c src/arch/arm/isa/decoder.isa
--- a/src/arch/arm/isa/decoder.isa Sat Nov 14 20:57:59 2009 -0800
+++ b/src/arch/arm/isa/decoder.isa Sat Nov 14 21:03:10 2009 -0800
@@ -115,31 +115,31 @@
}});
0x9: decode USEIMM {
// The mask field is the same as the RN index.
- 0: PredImmOp::msr_cpsr_imm({{
+ 0: PredOp::msr_cpsr_reg({{
+ uint32_t newCpsr =
+ cpsrWriteByInstr(Cpsr | CondCodes,
+ Rm, RN, false);
+ Cpsr = ~CondCodesMask & newCpsr;
+ CondCodes = CondCodesMask & newCpsr;
+ }});
+ 1: PredImmOp::msr_cpsr_imm({{
uint32_t newCpsr =
cpsrWriteByInstr(Cpsr | CondCodes,
rotated_imm, RN, false);
Cpsr = ~CondCodesMask & newCpsr;
CondCodes = CondCodesMask & newCpsr;
}});
- 1: PredOp::msr_cpsr_reg({{
- uint32_t newCpsr =
- cpsrWriteByInstr(Cpsr | CondCodes,
- Rm, RN, false);
- Cpsr = ~CondCodesMask & newCpsr;
- CondCodes = CondCodesMask & newCpsr;
- }});
}
0xa: PredOp::mrs_spsr({{ Rd = Spsr; }});
0xb: decode USEIMM {
// The mask field is the same as the RN index.
- 0: PredImmOp::msr_spsr_imm({{
+ 0: PredOp::msr_spsr_reg({{
+ Spsr = spsrWriteByInstr(Spsr, Rm, RN, false);
+ }});
+ 1: PredImmOp::msr_spsr_imm({{
Spsr = spsrWriteByInstr(Spsr, rotated_imm,
RN, false);
}});
- 1: PredOp::msr_spsr_reg({{
- Spsr = spsrWriteByInstr(Spsr, Rm, RN, false);
- }});
}
}
0x1: decode OPCODE {
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