changeset 71b272bd988e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=71b272bd988e
description:
ruby: included ruby config parameter ports per core
Slightly improved the major hack need to correctly assign the number of
ports
per core. CPUs have two ports: icache + dcache. MemTester has one
port.
diffstat:
5 files changed, 16 insertions(+), 8 deletions(-)
configs/example/memtest-ruby.py | 7 +++++--
src/mem/RubyMemory.py | 1 +
src/mem/rubymem.cc | 10 ++++++----
src/mem/rubymem.hh | 1 +
tests/configs/ruby_config.py | 5 +++--
diffs (86 lines):
diff -r 01202c147598 -r 71b272bd988e configs/example/memtest-ruby.py
--- a/configs/example/memtest-ruby.py Wed Nov 18 13:55:58 2009 -0800
+++ b/configs/example/memtest-ruby.py Wed Nov 18 13:55:58 2009 -0800
@@ -86,8 +86,11 @@
for i in xrange(options.testers) ]
# create the desired simulated system
-# ruby memory
-ruby_memory = ruby_config.generate("MI_example-homogeneous.rb",
options.testers)
+# ruby memory must be at least 16 MB to work with the mem tester
+ruby_memory = ruby_config.generate("MI_example-homogeneous.rb",
+ cores = options.testers,
+ memory_size = 16,
+ ports_per_cpu = 1)
system = System(cpu = cpus, funcmem = PhysicalMemory(),
physmem = ruby_memory)
diff -r 01202c147598 -r 71b272bd988e src/mem/RubyMemory.py
--- a/src/mem/RubyMemory.py Wed Nov 18 13:55:58 2009 -0800
+++ b/src/mem/RubyMemory.py Wed Nov 18 13:55:58 2009 -0800
@@ -45,3 +45,4 @@
num_dmas = Param.Int(0, "Number of DMA ports connected to the Ruby memory")
dma_port = VectorPort("Ruby_dma_ports")
pio_port = Port("Ruby_pio_port")
+ ports_per_core = Param.Int(2, "Number of per core. Typical two: icache +
dcache")
diff -r 01202c147598 -r 71b272bd988e src/mem/rubymem.cc
--- a/src/mem/rubymem.cc Wed Nov 18 13:55:58 2009 -0800
+++ b/src/mem/rubymem.cc Wed Nov 18 13:55:58 2009 -0800
@@ -58,6 +58,8 @@
ruby_clock = p->clock;
ruby_phase = p->phase;
+ ports_per_cpu = p->ports_per_core;
+
DPRINTF(Ruby, "creating Ruby Memory from file %s\n",
p->config_file.c_str());
@@ -230,14 +232,14 @@
//
// Currently this code assumes that each cpu has both a
- // icache and dcache port and therefore divides by two. This will be
- // fixed once we unify the configuration systems and Ruby sequencers
+ // icache and dcache port and therefore divides by ports per cpu. This
will
+ // be fixed once we unify the configuration systems and Ruby sequencers
// directly support M5 ports.
//
- assert(idx/2 < ruby_ports.size());
+ assert(idx/ports_per_cpu < ruby_ports.size());
Port *port = new Port(csprintf("%s-port%d", name(), idx),
this,
- ruby_ports[idx/2]);
+ ruby_ports[idx/ports_per_cpu]);
ports[idx] = port;
return port;
diff -r 01202c147598 -r 71b272bd988e src/mem/rubymem.hh
--- a/src/mem/rubymem.hh Wed Nov 18 13:55:58 2009 -0800
+++ b/src/mem/rubymem.hh Wed Nov 18 13:55:58 2009 -0800
@@ -130,6 +130,7 @@
Tick ruby_clock;
Tick ruby_phase;
RubyExitCallback* rubyExitCB;
+ int ports_per_cpu;
public:
static std::map<int64_t, PacketPtr> pending_requests;
diff -r 01202c147598 -r 71b272bd988e tests/configs/ruby_config.py
--- a/tests/configs/ruby_config.py Wed Nov 18 13:55:58 2009 -0800
+++ b/tests/configs/ruby_config.py Wed Nov 18 13:55:58 2009 -0800
@@ -8,7 +8,7 @@
def generate(config_file, cores=1, memories=1, memory_size=1024, \
cache_size=32768, cache_assoc=8, dmas=1,
- ruby_tick='1t'):
+ ruby_tick='1t', ports_per_cpu=2):
default = joinpath(dirname(__file__), '../../src/mem/ruby/config')
ruby_config = os.environ.get('RUBY_CONFIG', default)
args = [ "ruby", "-I", ruby_config, joinpath(ruby_config, "print_cfg.rb"),
@@ -25,4 +25,5 @@
config_file = temp_config,
num_cpus = cores,
range = AddrRange(str(memory_size)+"MB"),
- num_dmas = dmas)
+ num_dmas = dmas,
+ ports_per_core = ports_per_cpu)
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