Thanks Derek. Again, there is no big rush. I understand you have an important appointment at the Kohl Center tonight. J
Go Badgers…beat Duke! Brad From: [email protected] [mailto:[email protected]] On Behalf Of Derek Hower Sent: Tuesday, December 01, 2009 11:36 PM To: M5 Developer List Subject: Re: [m5-dev] Sequencer Usage of the AbstractController Pointer Hey Brad- I'll be checking it in asap. Unfortunately I didn't get a chance to do it before thanksgiving but it's high on the list as soon as I get back. -Derek On Dec 1, 2009, at 5:27 PM, "Beckmann, Brad" <[email protected]> wrote: Thanks Polina. No rush, but when do you suspect you’ll check in that code? Steve and I have made a lot of progress on the unified configuration changes and I’m hoping to send out another series of patches by the end of the week. I want to make sure our changes merge well with your updates and I’m willing to delay our patches to do so. Just let me know. Thanks again, Brad From: [email protected] [mailto:[email protected]] On Behalf Of Polina Dudnik Sent: Tuesday, December 01, 2009 12:16 PM To: M5 Developer List Subject: Re: [m5-dev] Sequencer Usage of the AbstractController Pointer Hi Brad, Yes, the new atomic support also requires the sequencer to have a pointer to the cache controller. The code that is in the repository now is a hack of the slicc protocol code generator. The code is inserted in the middle of the wakeup function in the cache controller. The new uncommited code instead specifies several functions for the cache controller, so that instead the Sequencer calls those functions upon encountering atomics. It is better this way because the Sequencer has much more useful information about the atomic and so it is easier for it to make a decision. All in all, the Sequencer needs to call the controller because the atomic operations block access to a specific cache block for a specific cache controller. It is harder to block the access anywhere else other than the cache controller. Hope this helps. Polina On Tue, Dec 1, 2009 at 2:08 PM, Beckmann, Brad <[email protected]> wrote: Hi, This question is mostly for Derek, but I figured that others at Wisconsin may be able to answer it as well. I notice that the current Ruby atomic support requires the sequencer to have direct access to its associated L1 cache controller, rather than just via the mandatory queue. Derek recently told me that he has some changes to how atomics are supported in Ruby. Does that new atomic support also require the sequencer to have a pointer to the cache controller? The reason I ask is it impacts the new unified configuration support. We can make it work as is, I just wanted to confirm that the effort was worth it. Thanks, Brad _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
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