changeset 353726c415f4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=353726c415f4
description:
        X86: Add a common named flag for signed media operations.

diffstat:

15 files changed, 158 insertions(+), 147 deletions(-)
src/arch/x86/insts/micromediaop.hh                                              
       |    7 +
src/arch/x86/isa/insts/simd128/integer/arithmetic/addition.py                   
       |   24 +--
src/arch/x86/isa/insts/simd128/integer/arithmetic/multiplication.py             
       |   24 +--
src/arch/x86/isa/insts/simd128/integer/arithmetic/multiply_add.py               
       |   24 +--
src/arch/x86/isa/insts/simd128/integer/arithmetic/subtraction.py                
       |   24 +--
src/arch/x86/isa/insts/simd128/integer/compare/compare_and_write_minimum_or_maximum.py
 |   24 +--
src/arch/x86/isa/insts/simd128/integer/data_reordering/pack_with_saturation.py  
       |   28 ++--
src/arch/x86/isa/insts/simd64/integer/arithmetic/addition.py                    
       |   12 -
src/arch/x86/isa/insts/simd64/integer/arithmetic/multiplication.py              
       |   18 +-
src/arch/x86/isa/insts/simd64/integer/arithmetic/multiply_add.py                
       |   12 -
src/arch/x86/isa/insts/simd64/integer/arithmetic/subtraction.py                 
       |   12 -
src/arch/x86/isa/insts/simd64/integer/compare/compare_and_write_minimum_or_maximum.py
  |   12 -
src/arch/x86/isa/insts/simd64/integer/data_reordering/pack_with_saturation.py   
       |   12 -
src/arch/x86/isa/microasm.isa                                                   
       |    2 
src/arch/x86/isa/microops/mediaop.isa                                           
       |   70 +++++-----

diffs (truncated from 800 to 300 lines):

diff -r 335f8b406bb9 -r 353726c415f4 src/arch/x86/insts/micromediaop.hh
--- a/src/arch/x86/insts/micromediaop.hh        Sat Dec 19 01:48:07 2009 -0800
+++ b/src/arch/x86/insts/micromediaop.hh        Sat Dec 19 01:48:31 2009 -0800
@@ -37,6 +37,7 @@
 {
     enum MediaFlag {
         MediaMultHiOp = 1,
+        MediaSignedOp = 64,
         MediaScalarOp = 128
     };
 
@@ -82,6 +83,12 @@
         {
             return ext & MediaMultHiOp;
         }
+
+        bool
+        signedOp() const
+        {
+            return ext & MediaSignedOp;
+        }
     };
 
     class MediaOpReg : public MediaOpBase
diff -r 335f8b406bb9 -r 353726c415f4 
src/arch/x86/isa/insts/simd128/integer/arithmetic/addition.py
--- a/src/arch/x86/isa/insts/simd128/integer/arithmetic/addition.py     Sat Dec 
19 01:48:07 2009 -0800
+++ b/src/arch/x86/isa/insts/simd128/integer/arithmetic/addition.py     Sat Dec 
19 01:48:31 2009 -0800
@@ -135,43 +135,43 @@
 };
 
 def macroop PADDSB_XMM_XMM {
-    maddi xmml, xmml, xmmlm, size=1, ext=4
-    maddi xmmh, xmmh, xmmhm, size=1, ext=4
+    maddi xmml, xmml, xmmlm, size=1, ext = "2 |" + Signed
+    maddi xmmh, xmmh, xmmhm, size=1, ext = "2 |" + Signed
 };
 
 def macroop PADDSB_XMM_M {
     ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8
     ldfp ufp2, seg, sib, "DISPLACEMENT + 8", dataSize=8
-    maddi xmml, xmml, ufp1, size=1, ext=4
-    maddi xmmh, xmmh, ufp2, size=1, ext=4
+    maddi xmml, xmml, ufp1, size=1, ext = "2 |" + Signed
+    maddi xmmh, xmmh, ufp2, size=1, ext = "2 |" + Signed
 };
 
 def macroop PADDSB_XMM_P {
     rdip t7
     ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8
     ldfp ufp2, seg, riprel, "DISPLACEMENT + 8", dataSize=8
-    maddi xmml, xmml, ufp1, size=1, ext=4
-    maddi xmmh, xmmh, ufp2, size=1, ext=4
+    maddi xmml, xmml, ufp1, size=1, ext = "2 |" + Signed
+    maddi xmmh, xmmh, ufp2, size=1, ext = "2 |" + Signed
 };
 
 def macroop PADDSW_XMM_XMM {
-    maddi xmml, xmml, xmmlm, size=2, ext=4
-    maddi xmmh, xmmh, xmmhm, size=2, ext=4
+    maddi xmml, xmml, xmmlm, size=2, ext = "2 |" + Signed
+    maddi xmmh, xmmh, xmmhm, size=2, ext = "2 |" + Signed
 };
 
 def macroop PADDSW_XMM_M {
     ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8
     ldfp ufp2, seg, sib, "DISPLACEMENT + 8", dataSize=8
-    maddi xmml, xmml, ufp1, size=2, ext=4
-    maddi xmmh, xmmh, ufp2, size=2, ext=4
+    maddi xmml, xmml, ufp1, size=2, ext = "2 |" + Signed
+    maddi xmmh, xmmh, ufp2, size=2, ext = "2 |" + Signed
 };
 
 def macroop PADDSW_XMM_P {
     rdip t7
     ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8
     ldfp ufp2, seg, riprel, "DISPLACEMENT + 8", dataSize=8
-    maddi xmml, xmml, ufp1, size=2, ext=4
-    maddi xmmh, xmmh, ufp2, size=2, ext=4
+    maddi xmml, xmml, ufp1, size=2, ext = "2 |" + Signed
+    maddi xmmh, xmmh, ufp2, size=2, ext = "2 |" + Signed
 };
 
 def macroop PADDUSB_XMM_XMM {
diff -r 335f8b406bb9 -r 353726c415f4 
src/arch/x86/isa/insts/simd128/integer/arithmetic/multiplication.py
--- a/src/arch/x86/isa/insts/simd128/integer/arithmetic/multiplication.py       
Sat Dec 19 01:48:07 2009 -0800
+++ b/src/arch/x86/isa/insts/simd128/integer/arithmetic/multiplication.py       
Sat Dec 19 01:48:31 2009 -0800
@@ -55,43 +55,43 @@
 
 microcode = '''
 def macroop PMULHW_XMM_XMM {
-    mmuli xmml, xmml, xmmlm, size=2, ext = "0x2 |" + MultHi
-    mmuli xmmh, xmmh, xmmhm, size=2, ext = "0x2 |" + MultHi
+    mmuli xmml, xmml, xmmlm, size=2, ext = Signed + "|" + MultHi
+    mmuli xmmh, xmmh, xmmhm, size=2, ext = Signed + "|" + MultHi
 };
 
 def macroop PMULHW_XMM_M {
     ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8
     ldfp ufp2, seg, sib, "DISPLACEMENT + 8", dataSize=8
-    mmuli xmml, xmml, ufp1, size=2, ext = "0x2 |" + MultHi
-    mmuli xmmh, xmmh, ufp2, size=2, ext = "0x2 |" + MultHi
+    mmuli xmml, xmml, ufp1, size=2, ext = Signed + "|" + MultHi
+    mmuli xmmh, xmmh, ufp2, size=2, ext = Signed + "|" + MultHi
 };
 
 def macroop PMULHW_XMM_P {
     rdip t7
     ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8
     ldfp ufp2, seg, riprel, "DISPLACEMENT + 8", dataSize=8
-    mmuli xmml, xmml, ufp1, size=2, ext = "0x2 |" + MultHi
-    mmuli xmmh, xmmh, ufp2, size=2, ext = "0x2 |" + MultHi
+    mmuli xmml, xmml, ufp1, size=2, ext = Signed + "|" + MultHi
+    mmuli xmmh, xmmh, ufp2, size=2, ext = Signed + "|" + MultHi
 };
 
 def macroop PMULLW_XMM_XMM {
-    mmuli xmml, xmml, xmmlm, size=2, ext=2
-    mmuli xmmh, xmmh, xmmhm, size=2, ext=2
+    mmuli xmml, xmml, xmmlm, size=2, ext=Signed
+    mmuli xmmh, xmmh, xmmhm, size=2, ext=Signed
 };
 
 def macroop PMULLW_XMM_M {
     ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8
     ldfp ufp2, seg, sib, "DISPLACEMENT + 8", dataSize=8
-    mmuli xmml, xmml, ufp1, size=2, ext=2
-    mmuli xmmh, xmmh, ufp2, size=2, ext=2
+    mmuli xmml, xmml, ufp1, size=2, ext=Signed
+    mmuli xmmh, xmmh, ufp2, size=2, ext=Signed
 };
 
 def macroop PMULLW_XMM_P {
     rdip t7
     ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8
     ldfp ufp2, seg, riprel, "DISPLACEMENT + 8", dataSize=8
-    mmuli xmml, xmml, ufp1, size=2, ext=2
-    mmuli xmmh, xmmh, ufp2, size=2, ext=2
+    mmuli xmml, xmml, ufp1, size=2, ext=Signed
+    mmuli xmmh, xmmh, ufp2, size=2, ext=Signed
 };
 
 def macroop PMULHUW_XMM_XMM {
diff -r 335f8b406bb9 -r 353726c415f4 
src/arch/x86/isa/insts/simd128/integer/arithmetic/multiply_add.py
--- a/src/arch/x86/isa/insts/simd128/integer/arithmetic/multiply_add.py Sat Dec 
19 01:48:07 2009 -0800
+++ b/src/arch/x86/isa/insts/simd128/integer/arithmetic/multiply_add.py Sat Dec 
19 01:48:31 2009 -0800
@@ -55,22 +55,22 @@
 
 microcode = '''
 def macroop PMADDWD_XMM_XMM {
-    mmuli ufp3, xmml, xmmlm, srcSize=2, destSize=4, ext=(0x2 | 0x10 | 0x20)
-    mmuli ufp4, xmml, xmmlm, srcSize=2, destSize=4, ext=(0x2 | 0x10)
+    mmuli ufp3, xmml, xmmlm, srcSize=2, destSize=4, ext = Signed + "| 0x10 | 
0x20"
+    mmuli ufp4, xmml, xmmlm, srcSize=2, destSize=4, ext = Signed + "| 0x10"
     maddi xmml, ufp3, ufp4, size=4, ext=0
-    mmuli ufp3, xmmh, xmmhm, srcSize=2, destSize=4, ext=(0x2 | 0x10 | 0x20)
-    mmuli ufp4, xmmh, xmmhm, srcSize=2, destSize=4, ext=(0x2 | 0x10)
+    mmuli ufp3, xmmh, xmmhm, srcSize=2, destSize=4, ext = Signed + "| 0x10 | 
0x20"
+    mmuli ufp4, xmmh, xmmhm, srcSize=2, destSize=4, ext = Signed + "| 0x10"
     maddi xmmh, ufp3, ufp4, size=4, ext=0
 };
 
 def macroop PMADDWD_XMM_M {
     ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8
     ldfp ufp2, seg, sib, "DISPLACEMENT + 8", dataSize=8
-    mmuli ufp3, xmml, ufp1, srcSize=2, destSize=4, ext=(0x2 | 0x10 | 0x20)
-    mmuli ufp4, xmml, ufp1, srcSize=2, destSize=4, ext=(0x2 | 0x10)
+    mmuli ufp3, xmml, ufp1, srcSize=2, destSize=4, ext = Signed + "| 0x10 | 
0x20"
+    mmuli ufp4, xmml, ufp1, srcSize=2, destSize=4, ext = Signed + "| 0x10"
     maddi xmml, ufp3, ufp4, size=4, ext=0
-    mmuli ufp3, xmmh, ufp2, srcSize=2, destSize=4, ext=(0x2 | 0x10 | 0x20)
-    mmuli ufp4, xmmh, ufp2, srcSize=2, destSize=4, ext=(0x2 | 0x10)
+    mmuli ufp3, xmmh, ufp2, srcSize=2, destSize=4, ext = Signed + "| 0x10 | 
0x20"
+    mmuli ufp4, xmmh, ufp2, srcSize=2, destSize=4, ext = Signed + "| 0x10"
     maddi xmmh, ufp3, ufp4, size=4, ext=0
 };
 
@@ -78,11 +78,11 @@
     rdip t7
     ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8
     ldfp ufp2, seg, riprel, "DISPLACEMENT + 8", dataSize=8
-    mmuli ufp3, xmml, ufp1, srcSize=2, destSize=4, ext=(0x2 | 0x10 | 0x20)
-    mmuli ufp4, xmml, ufp1, srcSize=2, destSize=4, ext=(0x2 | 0x10)
+    mmuli ufp3, xmml, ufp1, srcSize=2, destSize=4, ext = Signed + "| 0x10 | 
0x20"
+    mmuli ufp4, xmml, ufp1, srcSize=2, destSize=4, ext = Signed + "| 0x10"
     maddi xmml, ufp3, ufp4, size=4, ext=0
-    mmuli ufp3, xmmh, ufp2, srcSize=2, destSize=4, ext=(0x2 | 0x10 | 0x20)
-    mmuli ufp4, xmmh, ufp2, srcSize=2, destSize=4, ext=(0x2 | 0x10)
+    mmuli ufp3, xmmh, ufp2, srcSize=2, destSize=4, ext = Signed + "| 0x10 | 
0x20"
+    mmuli ufp4, xmmh, ufp2, srcSize=2, destSize=4, ext = Signed + "| 0x10"
     maddi xmmh, ufp3, ufp4, size=4, ext=0
 };
 '''
diff -r 335f8b406bb9 -r 353726c415f4 
src/arch/x86/isa/insts/simd128/integer/arithmetic/subtraction.py
--- a/src/arch/x86/isa/insts/simd128/integer/arithmetic/subtraction.py  Sat Dec 
19 01:48:07 2009 -0800
+++ b/src/arch/x86/isa/insts/simd128/integer/arithmetic/subtraction.py  Sat Dec 
19 01:48:31 2009 -0800
@@ -135,43 +135,43 @@
 };
 
 def macroop PSUBSB_XMM_XMM {
-    msubi xmml, xmml, xmmlm, size=1, ext=4
-    msubi xmmh, xmmh, xmmhm, size=1, ext=4
+    msubi xmml, xmml, xmmlm, size=1, ext = "2 |" + Signed
+    msubi xmmh, xmmh, xmmhm, size=1, ext = "2 |" + Signed
 };
 
 def macroop PSUBSB_XMM_M {
     ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8
     ldfp ufp2, seg, sib, "DISPLACEMENT + 8", dataSize=8
-    msubi xmml, xmml, ufp1, size=1, ext=4
-    msubi xmmh, xmmh, ufp2, size=1, ext=4
+    msubi xmml, xmml, ufp1, size=1, ext = "2 |" + Signed
+    msubi xmmh, xmmh, ufp2, size=1, ext = "2 |" + Signed
 };
 
 def macroop PSUBSB_XMM_P {
     rdip t7
     ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8
     ldfp ufp2, seg, riprel, "DISPLACEMENT + 8", dataSize=8
-    msubi xmml, xmml, ufp1, size=1, ext=4
-    msubi xmmh, xmmh, ufp2, size=1, ext=4
+    msubi xmml, xmml, ufp1, size=1, ext = "2 |" + Signed
+    msubi xmmh, xmmh, ufp2, size=1, ext = "2 |" + Signed
 };
 
 def macroop PSUBSW_XMM_XMM {
-    msubi xmml, xmml, xmmlm, size=2, ext=4
-    msubi xmmh, xmmh, xmmhm, size=2, ext=4
+    msubi xmml, xmml, xmmlm, size=2, ext = "2 |" + Signed
+    msubi xmmh, xmmh, xmmhm, size=2, ext = "2 |" + Signed
 };
 
 def macroop PSUBSW_XMM_M {
     ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8
     ldfp ufp2, seg, sib, "DISPLACEMENT + 8", dataSize=8
-    msubi xmml, xmml, ufp1, size=2, ext=4
-    msubi xmmh, xmmh, ufp2, size=2, ext=4
+    msubi xmml, xmml, ufp1, size=2, ext = "2 |" + Signed
+    msubi xmmh, xmmh, ufp2, size=2, ext = "2 |" + Signed
 };
 
 def macroop PSUBSW_XMM_P {
     rdip t7
     ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8
     ldfp ufp2, seg, riprel, "DISPLACEMENT + 8", dataSize=8
-    msubi xmml, xmml, ufp1, size=2, ext=4
-    msubi xmmh, xmmh, ufp2, size=2, ext=4
+    msubi xmml, xmml, ufp1, size=2, ext = "2 |" + Signed
+    msubi xmmh, xmmh, ufp2, size=2, ext = "2 |" + Signed
 };
 
 def macroop PSUBUSB_XMM_XMM {
diff -r 335f8b406bb9 -r 353726c415f4 
src/arch/x86/isa/insts/simd128/integer/compare/compare_and_write_minimum_or_maximum.py
--- 
a/src/arch/x86/isa/insts/simd128/integer/compare/compare_and_write_minimum_or_maximum.py
    Sat Dec 19 01:48:07 2009 -0800
+++ 
b/src/arch/x86/isa/insts/simd128/integer/compare/compare_and_write_minimum_or_maximum.py
    Sat Dec 19 01:48:31 2009 -0800
@@ -75,23 +75,23 @@
 };
 
 def macroop PMINSW_XMM_XMM {
-    mmini xmml, xmml, xmmlm, size=2, ext=2
-    mmini xmmh, xmmh, xmmhm, size=2, ext=2
+    mmini xmml, xmml, xmmlm, size=2, ext=Signed
+    mmini xmmh, xmmh, xmmhm, size=2, ext=Signed
 };
 
 def macroop PMINSW_XMM_M {
     ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8
     ldfp ufp2, seg, sib, "DISPLACEMENT + 8", dataSize=8
-    mmini xmml, xmml, ufp1, size=2, ext=2
-    mmini xmmh, xmmh, ufp2, size=2, ext=2
+    mmini xmml, xmml, ufp1, size=2, ext=Signed
+    mmini xmmh, xmmh, ufp2, size=2, ext=Signed
 };
 
 def macroop PMINSW_XMM_P {
     rdip t7
     ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8
     ldfp ufp2, seg, riprel, "DISPLACEMENT + 8", dataSize=8
-    mmini xmml, xmml, ufp1, size=2, ext=2
-    mmini xmmh, xmmh, ufp2, size=2, ext=2
+    mmini xmml, xmml, ufp1, size=2, ext=Signed
+    mmini xmmh, xmmh, ufp2, size=2, ext=Signed
 };
 
 def macroop PMAXUB_XMM_XMM {
@@ -115,22 +115,22 @@
 };
 
 def macroop PMAXSW_XMM_XMM {
-    mmaxi xmml, xmml, xmmlm, size=2, ext=2
-    mmaxi xmmh, xmmh, xmmhm, size=2, ext=2
+    mmaxi xmml, xmml, xmmlm, size=2, ext=Signed
+    mmaxi xmmh, xmmh, xmmhm, size=2, ext=Signed
 };
 
 def macroop PMAXSW_XMM_M {
     ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8
     ldfp ufp2, seg, sib, "DISPLACEMENT + 8", dataSize=8
-    mmaxi xmml, xmml, ufp1, size=2, ext=2
-    mmaxi xmmh, xmmh, ufp2, size=2, ext=2
+    mmaxi xmml, xmml, ufp1, size=2, ext=Signed
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