changeset 45879b0e3240 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=45879b0e3240
description:
MIPS: Extract CPU pointer from the thread context in scheduleCP0
setMiscReg.
The MIPS ISA object expects to be constructed with a CPU pointer it
uses to
look at other thread contexts and allow them to be manipulated with
control
registers. Unfortunately, that differs from all the other ISA classes
and
would complicate their implementation.
This change makes the event constructor use a CPU pointer pulled out of
the
thread context passed to setMiscReg instead.
diffstat:
2 files changed, 8 insertions(+), 18 deletions(-)
src/arch/mips/isa.cc | 17 +++++------------
src/arch/mips/isa.hh | 9 +++------
diffs (102 lines):
diff -r aa9e72a7d8d3 -r 45879b0e3240 src/arch/mips/isa.cc
--- a/src/arch/mips/isa.cc Mon Dec 21 14:59:40 2009 -0800
+++ b/src/arch/mips/isa.cc Thu Dec 31 15:30:50 2009 -0500
@@ -91,12 +91,6 @@
init();
}
-ISA::ISA(BaseCPU *_cpu)
-{
- cpu = _cpu;
- init();
-}
-
void
ISA::init()
{
@@ -173,11 +167,10 @@
//@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H)
void
ISA::reset(std::string core_name, ThreadID num_threads,
- unsigned num_vpes, BaseCPU *_cpu)
+ unsigned num_vpes, BaseCPU *cpu)
{
DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n",
num_threads, num_vpes);
- cpu = _cpu;
MipsISA::CoreSpecific &cp = cpu->coreParams;
@@ -499,7 +492,7 @@
miscRegFile[misc_reg][reg_sel] = cp0_val;
- scheduleCP0Update(1);
+ scheduleCP0Update(tc->getCpuPtr(), 1);
}
/**
@@ -528,7 +521,7 @@
}
void
-ISA::scheduleCP0Update(int delay)
+ISA::scheduleCP0Update(BaseCPU *cpu, int delay)
{
if (!cp0Updated) {
cp0Updated = true;
@@ -540,7 +533,7 @@
}
void
-ISA::updateCPU()
+ISA::updateCPU(BaseCPU *cpu)
{
///////////////////////////////////////////////////////////////////
//
@@ -578,7 +571,7 @@
switch (cp0EventType)
{
case UpdateCP0:
- cp0->updateCPU();
+ cp0->updateCPU(cpu);
break;
}
}
diff -r aa9e72a7d8d3 -r 45879b0e3240 src/arch/mips/isa.hh
--- a/src/arch/mips/isa.hh Mon Dec 21 14:59:40 2009 -0800
+++ b/src/arch/mips/isa.hh Thu Dec 31 15:30:50 2009 -0500
@@ -64,18 +64,15 @@
std::vector<std::vector<MiscReg> > miscRegFile_WriteMask;
std::vector<BankType> bankType;
- BaseCPU *cpu;
-
public:
ISA();
- ISA(BaseCPU *_cpu);
void init();
void clear(unsigned tid_or_vpn = 0);
void reset(std::string core_name, ThreadID num_threads,
- unsigned num_vpes, BaseCPU *_cpu);
+ unsigned num_vpes, BaseCPU *cpu);
void expandForMultithreading(ThreadID num_threads, unsigned num_vpes);
@@ -147,11 +144,11 @@
};
// Schedule a CP0 Update Event
- void scheduleCP0Update(int delay = 0);
+ void scheduleCP0Update(BaseCPU *cpu, int delay = 0);
// If any changes have been made, then check the state for changes
// and if necessary alert the CPU
- void updateCPU();
+ void updateCPU(BaseCPU *cpu);
// Keep a List of CPU Events that need to be deallocated
std::queue<CP0Event*> cp0EventRemoveList;
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