[m5-dev] [PATCH 37 of 41] ruby: fixed memory fetch bug for persistent requests

[Brad Beckmann]

# HG changeset patch
# User Brad Beckmann <brad.beckm...@amd.com>
# Date 1263536247 28800
# Node ID 01c7f6873059e7daa8f7fd00e5c39cbf60c2e409
# Parent  061151fda49a35f2d8ba4a20d2ed159c9ed23493
ruby: fixed memory fetch bug for persistent requests

diff -r 061151fda49a -r 01c7f6873059 src/mem/protocol/MOESI_CMP_token-dir.sm
--- a/src/mem/protocol/MOESI_CMP_token-dir.sm   Thu Jan 14 22:17:27 2010 -0800
+++ b/src/mem/protocol/MOESI_CMP_token-dir.sm   Thu Jan 14 22:17:27 2010 -0800
@@ -61,7 +61,8 @@
 
     // Memory wait states - can block all messages including persistent 
requests
     O_W, desc="transitioning to Owner, waiting for memory write";
-    L_W, desc="transitioning to Locked, waiting for memory read";
+    L_O_W, desc="transitioning to Locked, waiting for memory read, could 
eventually return to O";
+    L_NO_W, desc="transitioning to Locked, waiting for memory read, eventually 
return to NO";
     DR_L_W, desc="transitioning to Locked underneath a DMA read, waiting for 
memory data";
     NO_W, desc="transitioning to Not Owner, waiting for memory read";
     O_DW_W, desc="transitioning to Owner, waiting for memory before DMA ack";
@@ -571,6 +572,18 @@
     }
   }
 
+  action(qp_queueMemoryForPersistent, "qp", desc="Queue off-chip fetch 
request") {
+    enqueue(memQueue_out, MemoryMsg, latency="1") {
+      out_msg.Address := address;
+      out_msg.Type := MemoryRequestType:MEMORY_READ;
+      out_msg.Sender := machineID;
+      out_msg.OriginalRequestorMachId := persistentTable.findSmallest(address);
+      out_msg.MessageSize := MessageSizeType:Request_Control;
+      out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
+      DEBUG_EXPR(out_msg);
+    }
+  }
+
   action(fd_memoryDma, "fd", desc="Queue off-chip fetch request") {
     peek(dmaRequestQueue_in, DMARequestMsg) {    
       enqueue(memQueue_out, MemoryMsg, latency="1") {
@@ -868,8 +881,8 @@
     p_popDmaRequestQueue;
   }
 
-  transition(O, Lockdown, L_W) {
-    qf_queueMemoryFetchRequest;
+  transition(O, Lockdown, L_O_W) {
+    qp_queueMemoryForPersistent;
     l_popIncomingPersistentQueue;
   }
 
@@ -1059,7 +1072,7 @@
     j_popIncomingRequestQueue;
   }
 
-  transition({L, DW_L, DR_L, L_W, DR_L_W}, Lockdown) {
+  transition({L, DW_L, DR_L, L_O_W, L_NO_W, DR_L_W}, Lockdown) {
     l_popIncomingPersistentQueue;
   }
 
@@ -1089,11 +1102,19 @@
     l_popIncomingPersistentQueue;
   }
 
-  transition(L_W, Memory_Data, L) {
+  transition({L_NO_W, L_O_W}, Memory_Data, L) {
     dd_sendDataWithAllTokensToStarver;
     l_popMemQueue;
   }
 
+  transition(L_O_W, {Unlockdown, Own_Lock_or_Unlock}, O_W) {
+    l_popIncomingPersistentQueue;
+  }
+
+  transition(L_NO_W, {Unlockdown, Own_Lock_or_Unlock}, NO_W) {
+    l_popIncomingPersistentQueue;
+  }
+
   transition(DR_L_W, Memory_Data, DR_L) {
     dd_sendDataWithAllTokensToStarver;
     l_popMemQueue;
@@ -1121,7 +1142,11 @@
     ps_tryIssuingPersistentGETSRequest;
   }
 
-  transition(O_W, Memory_Ack, O) {
+  //
+  // The O_W + Memory_Data > O transistion is confusing, but it can happen if a
+  // presistent request is issued and resolve before memory returns with data
+  //
+  transition(O_W, {Memory_Ack, Memory_Data}, O) {
     l_popMemQueue; 
   }
 
@@ -1130,19 +1155,23 @@
   }
 
   // Blocked states
-  transition({NO_W, O_W, L_W, DR_L_W, O_DW_W, O_DR_W, O_DW, NO_DW, NO_DR}, 
{GETX, GETS}) {
+  transition({NO_W, O_W, L_O_W, L_NO_W, DR_L_W, O_DW_W, O_DR_W, O_DW, NO_DW, 
NO_DR}, {GETX, GETS}) {
     z_recycleRequest;
   }
 
-  transition({NO_W, O_W, L_W, DR_L_W, O_DW_W, O_DR_W, O_DW, NO_DW, NO_DR, L, 
DW_L, DR_L}, {DMA_READ, DMA_WRITE}) {
+  transition({NO_W, O_W, L_O_W, L_NO_W, DR_L_W, O_DW_W, O_DR_W, O_DW, NO_DW, 
NO_DR, L, DW_L, DR_L}, {DMA_READ, DMA_WRITE}) {
     y_recycleDmaRequestQueue;
   }
 
-  transition({NO_W, O_W, L_W, DR_L_W, O_DW_W, O_DR_W}, {Data_Owner, Ack_Owner, 
Tokens}) {
+  transition({NO_W, O_W, L_O_W, L_NO_W, DR_L_W, O_DW_W, O_DR_W}, {Data_Owner, 
Ack_Owner, Tokens}) {
     kz_recycleResponse;
   }
 
-  transition({NO_W, O_W}, Lockdown, L_W) {
+  transition(NO_W, Lockdown, L_NO_W) {
+    l_popIncomingPersistentQueue;
+  }
+
+  transition(O_W, Lockdown, L_O_W) {
     l_popIncomingPersistentQueue;
   }
 

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