changeset 3c557ac2ca74 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=3c557ac2ca74 description: protocol: cleaned up MESI...got rid of unneccessary virtual networks
diffstat: 5 files changed, 59 insertions(+), 148 deletions(-) src/mem/protocol/MESI_CMP_directory-L1cache.sm | 14 +--- src/mem/protocol/MESI_CMP_directory-L2cache.sm | 10 +-- src/mem/protocol/MESI_CMP_directory-dma.sm | 36 ++++------ src/mem/protocol/MESI_CMP_directory-mem.sm | 79 +++++++++--------------- src/mem/protocol/MESI_CMP_directory-msg.sm | 68 -------------------- diffs (truncated from 431 to 300 lines): diff -r 1139f1e51da9 -r 3c557ac2ca74 src/mem/protocol/MESI_CMP_directory-L1cache.sm --- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm Fri Sep 25 17:51:12 2009 -0500 +++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm Fri Sep 25 17:51:51 2009 -0500 @@ -27,12 +27,6 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* - * $Id: MSI_MOSI_CMP_directory-L1cache.sm 1.10 05/01/19 15:55:40-06:00 [email protected] $ - * - */ - - machine(L1Cache, "MSI Directory L1 Cache CMP") : int l1_request_latency, int l1_response_latency, @@ -47,15 +41,15 @@ // a local L1 -> this L2 bank, currently ordered with directory forwarded requests MessageBuffer requestFromL1Cache, network="To", virtual_network="0", ordered="false"; // a local L1 -> this L2 bank - MessageBuffer responseFromL1Cache, network="To", virtual_network="3", ordered="false"; - MessageBuffer unblockFromL1Cache, network="To", virtual_network="4", ordered="false"; + MessageBuffer responseFromL1Cache, network="To", virtual_network="1", ordered="false"; + MessageBuffer unblockFromL1Cache, network="To", virtual_network="2", ordered="false"; // To this node's L1 cache FROM the network // a L2 bank -> this L1 - MessageBuffer requestToL1Cache, network="From", virtual_network="1", ordered="false"; + MessageBuffer requestToL1Cache, network="From", virtual_network="0", ordered="false"; // a L2 bank -> this L1 - MessageBuffer responseToL1Cache, network="From", virtual_network="3", ordered="false"; + MessageBuffer responseToL1Cache, network="From", virtual_network="1", ordered="false"; // STATES enumeration(State, desc="Cache states", default="L1Cache_State_I") { diff -r 1139f1e51da9 -r 3c557ac2ca74 src/mem/protocol/MESI_CMP_directory-L2cache.sm --- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm Fri Sep 25 17:51:12 2009 -0500 +++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm Fri Sep 25 17:51:51 2009 -0500 @@ -40,14 +40,14 @@ // L2 BANK QUEUES // From local bank of L2 cache TO the network - MessageBuffer DirRequestFromL2Cache, network="To", virtual_network="2", ordered="false"; // this L2 bank -> Memory - MessageBuffer L1RequestFromL2Cache, network="To", virtual_network="1", ordered="false"; // this L2 bank -> a local L1 - MessageBuffer responseFromL2Cache, network="To", virtual_network="3", ordered="false"; // this L2 bank -> a local L1 || Memory + MessageBuffer DirRequestFromL2Cache, network="To", virtual_network="0", ordered="false"; // this L2 bank -> Memory + MessageBuffer L1RequestFromL2Cache, network="To", virtual_network="0", ordered="false"; // this L2 bank -> a local L1 + MessageBuffer responseFromL2Cache, network="To", virtual_network="1", ordered="false"; // this L2 bank -> a local L1 || Memory // FROM the network to this local bank of L2 cache - MessageBuffer unblockToL2Cache, network="From", virtual_network="4", ordered="false"; // a local L1 || Memory -> this L2 bank + MessageBuffer unblockToL2Cache, network="From", virtual_network="2", ordered="false"; // a local L1 || Memory -> this L2 bank MessageBuffer L1RequestToL2Cache, network="From", virtual_network="0", ordered="false"; // a local L1 -> this L2 bank - MessageBuffer responseToL2Cache, network="From", virtual_network="3", ordered="false"; // a local L1 || Memory -> this L2 bank + MessageBuffer responseToL2Cache, network="From", virtual_network="1", ordered="false"; // a local L1 || Memory -> this L2 bank // MessageBuffer unblockToL2Cache, network="From", virtual_network="4", ordered="false"; // a local L1 || Memory -> this L2 bank // STATES diff -r 1139f1e51da9 -r 3c557ac2ca74 src/mem/protocol/MESI_CMP_directory-dma.sm --- a/src/mem/protocol/MESI_CMP_directory-dma.sm Fri Sep 25 17:51:12 2009 -0500 +++ b/src/mem/protocol/MESI_CMP_directory-dma.sm Fri Sep 25 17:51:51 2009 -0500 @@ -3,8 +3,8 @@ : int request_latency { - MessageBuffer responseFromDir, network="From", virtual_network="6", ordered="true", no_vector="true"; - MessageBuffer reqToDirectory, network="To", virtual_network="7", ordered="false", no_vector="true"; + MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", no_vector="true"; + MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", no_vector="true"; enumeration(State, desc="DMA states", default="DMA_State_READY") { READY, desc="Ready to accept a new request"; @@ -51,13 +51,13 @@ } } - in_port(dmaResponseQueue_in, DMAResponseMsg, responseFromDir, desc="...") { + in_port(dmaResponseQueue_in, ResponseMsg, responseFromDir, desc="...") { if (dmaResponseQueue_in.isReady()) { - peek( dmaResponseQueue_in, DMAResponseMsg) { - if (in_msg.Type == DMAResponseType:ACK) { - trigger(Event:Ack, in_msg.LineAddress); - } else if (in_msg.Type == DMAResponseType:DATA) { - trigger(Event:Data, in_msg.LineAddress); + peek( dmaResponseQueue_in, ResponseMsg) { + if (in_msg.Type == CoherenceResponseType:ACK) { + trigger(Event:Ack, makeLineAddress(in_msg.Address)); + } else if (in_msg.Type == CoherenceResponseType:DATA) { + trigger(Event:Data, makeLineAddress(in_msg.Address)); } else { error("Invalid response type"); } @@ -67,10 +67,9 @@ action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") { peek(dmaRequestQueue_in, SequencerMsg) { - enqueue(reqToDirectory_out, DMARequestMsg, latency=request_latency) { - out_msg.PhysicalAddress := in_msg.PhysicalAddress; - out_msg.LineAddress := in_msg.LineAddress; - out_msg.Type := DMARequestType:READ; + enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) { + out_msg.Address := in_msg.PhysicalAddress; + out_msg.Type := CoherenceRequestType:DMA_READ; out_msg.DataBlk := in_msg.DataBlk; out_msg.Len := in_msg.Len; out_msg.Destination.add(map_Address_to_Directory(address)); @@ -81,10 +80,9 @@ action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") { peek(dmaRequestQueue_in, SequencerMsg) { - enqueue(reqToDirectory_out, DMARequestMsg, latency=request_latency) { - out_msg.PhysicalAddress := in_msg.PhysicalAddress; - out_msg.LineAddress := in_msg.LineAddress; - out_msg.Type := DMARequestType:WRITE; + enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) { + out_msg.Address := in_msg.PhysicalAddress; + out_msg.Type := CoherenceRequestType:DMA_WRITE; out_msg.DataBlk := in_msg.DataBlk; out_msg.Len := in_msg.Len; out_msg.Destination.add(map_Address_to_Directory(address)); @@ -94,13 +92,11 @@ } action(a_ackCallback, "a", desc="Notify dma controller that write request completed") { - peek (dmaResponseQueue_in, DMAResponseMsg) { - dma_sequencer.ackCallback(); - } + dma_sequencer.ackCallback(); } action(d_dataCallback, "d", desc="Write data to dma sequencer") { - peek (dmaResponseQueue_in, DMAResponseMsg) { + peek (dmaResponseQueue_in, ResponseMsg) { dma_sequencer.dataCallback(in_msg.DataBlk); } } diff -r 1139f1e51da9 -r 3c557ac2ca74 src/mem/protocol/MESI_CMP_directory-mem.sm --- a/src/mem/protocol/MESI_CMP_directory-mem.sm Fri Sep 25 17:51:12 2009 -0500 +++ b/src/mem/protocol/MESI_CMP_directory-mem.sm Fri Sep 25 17:51:51 2009 -0500 @@ -40,13 +40,11 @@ int directory_latency { - MessageBuffer requestToDir, network="From", virtual_network="2", ordered="false"; - MessageBuffer responseToDir, network="From", virtual_network="3", ordered="false"; - MessageBuffer responseFromDir, network="To", virtual_network="3", ordered="false"; + MessageBuffer requestToDir, network="From", virtual_network="0", ordered="false"; + MessageBuffer responseToDir, network="From", virtual_network="1", ordered="false"; - MessageBuffer dmaRequestFromDir, network="To", virtual_network="6", ordered="true"; - MessageBuffer dmaRequestToDir, network="From", virtual_network="7", ordered="true"; - + MessageBuffer requestFromDir, network="To", virtual_network="0", ordered="false"; + MessageBuffer responseFromDir, network="To", virtual_network="1", ordered="false"; // STATES enumeration(State, desc="Directory states", default="Directory_State_I") { @@ -167,32 +165,19 @@ // ** OUT_PORTS ** out_port(responseNetwork_out, ResponseMsg, responseFromDir); out_port(memQueue_out, MemoryMsg, memBuffer); - out_port(dmaResponseNetwork_out, DMAResponseMsg, dmaRequestFromDir); // ** IN_PORTS ** -//added by SS for dma - in_port(dmaRequestQueue_in, DMARequestMsg, dmaRequestToDir) { - if (dmaRequestQueue_in.isReady()) { - peek(dmaRequestQueue_in, DMARequestMsg) { - if (in_msg.Type == DMARequestType:READ) { - trigger(Event:DMA_READ, in_msg.LineAddress); - } else if (in_msg.Type == DMARequestType:WRITE) { - trigger(Event:DMA_WRITE, in_msg.LineAddress); - } else { - error("Invalid message"); - } - } - } - } - - in_port(requestNetwork_in, RequestMsg, requestToDir) { if (requestNetwork_in.isReady()) { peek(requestNetwork_in, RequestMsg) { assert(in_msg.Destination.isElement(machineID)); if (isGETRequest(in_msg.Type)) { trigger(Event:Fetch, in_msg.Address); + } else if (in_msg.Type == CoherenceRequestType:DMA_READ) { + trigger(Event:DMA_READ, makeLineAddress(in_msg.Address)); + } else if (in_msg.Type == CoherenceRequestType:DMA_WRITE) { + trigger(Event:DMA_WRITE, makeLineAddress(in_msg.Address)); } else { DEBUG_EXPR(in_msg); error("Invalid message"); @@ -328,7 +313,7 @@ } //added by SS for dma action(qf_queueMemoryFetchRequestDMA, "qfd", desc="Queue off-chip fetch request") { - peek(dmaRequestQueue_in, DMARequestMsg) { + peek(requestNetwork_in, RequestMsg) { enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) { out_msg.Address := address; out_msg.Type := MemoryRequestType:MEMORY_READ; @@ -342,14 +327,14 @@ } action(p_popIncomingDMARequestQueue, "p", desc="Pop incoming DMA queue") { - dmaRequestQueue_in.dequeue(); + requestNetwork_in.dequeue(); } action(dr_sendDMAData, "dr", desc="Send Data to DMA controller from directory") { peek(memQueue_in, MemoryMsg) { - enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency=to_mem_ctrl_latency) { - out_msg.PhysicalAddress := address; - out_msg.Type := DMAResponseType:DATA; + enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) { + out_msg.Address := address; + out_msg.Type := CoherenceResponseType:DATA; out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be out_msg.Destination.add(map_Address_to_DMA(address)); out_msg.MessageSize := MessageSizeType:Response_Data; @@ -358,15 +343,13 @@ } action(dw_writeDMAData, "dw", desc="DMA Write data to memory") { - peek(dmaRequestQueue_in, DMARequestMsg) { - //directory[in_msg.PhysicalAddress].DataBlk.copyPartial(in_msg.DataBlk, in_msg.Offset, in_msg.Len); - - directory[in_msg.PhysicalAddress].DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.PhysicalAddress), in_msg.Len); + peek(requestNetwork_in, RequestMsg) { + directory[address].DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Address), in_msg.Len); } } action(qw_queueMemoryWBRequest_partial, "qwp", desc="Queue off-chip writeback request") { - peek(dmaRequestQueue_in, DMARequestMsg) { + peek(requestNetwork_in, RequestMsg) { enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) { out_msg.Address := address; out_msg.Type := MemoryRequestType:MEMORY_WB; @@ -384,9 +367,9 @@ } action(da_sendDMAAck, "da", desc="Send Ack to DMA controller") { - enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency=to_mem_ctrl_latency) { - out_msg.PhysicalAddress := address; - out_msg.Type := DMAResponseType:ACK; + enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) { + out_msg.Address := address; + out_msg.Type := CoherenceResponseType:ACK; out_msg.Destination.add(map_Address_to_DMA(address)); out_msg.MessageSize := MessageSizeType:Writeback_Control; } @@ -397,7 +380,7 @@ } action(zz_recycleDMAQueue, "zz", desc="recycle DMA queue") { - dmaRequestQueue_in.recycle(); + requestNetwork_in.recycle(); } @@ -410,12 +393,12 @@ action(inv_sendCacheInvalidate, "inv", desc="Invalidate a cache block") { - peek(dmaRequestQueue_in, DMARequestMsg) { + peek(requestNetwork_in, RequestMsg) { enqueue(responseNetwork_out, ResponseMsg, latency=directory_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:INV; out_msg.Sender := machineID; - out_msg.Destination := directory[in_msg.PhysicalAddress].Owner; + out_msg.Destination := directory[address].Owner; out_msg.MessageSize := MessageSizeType:Response_Control; } } @@ -424,9 +407,9 @@ action(drp_sendDMAData, "drp", desc="Send Data to DMA controller from incoming PUTX") { peek(responseNetwork_in, ResponseMsg) { - enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency=to_mem_ctrl_latency) { - out_msg.PhysicalAddress := address; - out_msg.Type := DMAResponseType:DATA; + enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) { + out_msg.Address := address; + out_msg.Type := CoherenceResponseType:DATA; out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be out_msg.Destination.add(map_Address_to_DMA(address)); out_msg.MessageSize := MessageSizeType:Response_Data; @@ -439,10 +422,10 @@ } action(v_allocateTBE, "v", desc="Allocate TBE") { - peek(dmaRequestQueue_in, DMARequestMsg) { + peek(requestNetwork_in, RequestMsg) { TBEs.allocate(address); TBEs[address].DataBlk := in_msg.DataBlk; _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
