changeset 40d2245c6679 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=40d2245c6679 description: memtest differences from Derek's changes
diffstat: 4 files changed, 3529 insertions(+), 637 deletions(-) tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats | 3964 ++++++++-- tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr | 148 tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout | 12 tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt | 42 diffs (truncated from 4606 to 300 lines): diff -r 21fbf0412e0d -r 40d2245c6679 tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats Tue Jan 19 17:11:36 2010 -0600 +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats Tue Jan 19 17:17:19 2010 -0600 @@ -12,189 +12,334 @@ memory_size_bits: 30 DMA_Controller config: DMAController_0 version: 0 - buffer_size: 0 + buffer_size: 32 dma_sequencer: DMASequencer_0 number_of_TBEs: 256 recycle_latency: 10 - request_latency: 6 + request_latency: 14 + response_latency: 14 transitions_per_cycle: 32 Directory_Controller config: DirectoryController_0 version: 0 - buffer_size: 0 + buffer_size: 32 + directory: DirectoryMemory_0 directory_latency: 6 - directory_name: DirectoryMemory_0 - memory_controller_name: MemoryControl_0 + memory_control: MemoryControl_0 number_of_TBEs: 256 recycle_latency: 10 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_0 version: 0 - buffer_size: 0 - cache: l1u_0 - cache_response_latency: 12 - issue_latency: 2 + buffer_size: 32 + dcache: l1d_0 + icache: l1i_0 + l2_select_low_bit: 6 + l2_select_num_bits: 1 number_of_TBEs: 256 recycle_latency: 10 + request_latency: 2 sequencer: Sequencer_0 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_1 version: 1 - buffer_size: 0 - cache: l1u_1 - cache_response_latency: 12 - issue_latency: 2 + buffer_size: 32 + dcache: l1d_1 + icache: l1i_1 + l2_select_low_bit: 6 + l2_select_num_bits: 1 number_of_TBEs: 256 recycle_latency: 10 + request_latency: 2 sequencer: Sequencer_1 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_2 version: 2 - buffer_size: 0 - cache: l1u_2 - cache_response_latency: 12 - issue_latency: 2 + buffer_size: 32 + dcache: l1d_2 + icache: l1i_2 + l2_select_low_bit: 6 + l2_select_num_bits: 1 number_of_TBEs: 256 recycle_latency: 10 + request_latency: 2 sequencer: Sequencer_2 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_3 version: 3 - buffer_size: 0 - cache: l1u_3 - cache_response_latency: 12 - issue_latency: 2 + buffer_size: 32 + dcache: l1d_3 + icache: l1i_3 + l2_select_low_bit: 6 + l2_select_num_bits: 1 number_of_TBEs: 256 recycle_latency: 10 + request_latency: 2 sequencer: Sequencer_3 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_4 version: 4 - buffer_size: 0 - cache: l1u_4 - cache_response_latency: 12 - issue_latency: 2 + buffer_size: 32 + dcache: l1d_4 + icache: l1i_4 + l2_select_low_bit: 6 + l2_select_num_bits: 1 number_of_TBEs: 256 recycle_latency: 10 + request_latency: 2 sequencer: Sequencer_4 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_5 version: 5 - buffer_size: 0 - cache: l1u_5 - cache_response_latency: 12 - issue_latency: 2 + buffer_size: 32 + dcache: l1d_5 + icache: l1i_5 + l2_select_low_bit: 6 + l2_select_num_bits: 1 number_of_TBEs: 256 recycle_latency: 10 + request_latency: 2 sequencer: Sequencer_5 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_6 version: 6 - buffer_size: 0 - cache: l1u_6 - cache_response_latency: 12 - issue_latency: 2 + buffer_size: 32 + dcache: l1d_6 + icache: l1i_6 + l2_select_low_bit: 6 + l2_select_num_bits: 1 number_of_TBEs: 256 recycle_latency: 10 + request_latency: 2 sequencer: Sequencer_6 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_7 version: 7 - buffer_size: 0 - cache: l1u_7 - cache_response_latency: 12 - issue_latency: 2 + buffer_size: 32 + dcache: l1d_7 + icache: l1i_7 + l2_select_low_bit: 6 + l2_select_num_bits: 1 number_of_TBEs: 256 recycle_latency: 10 + request_latency: 2 sequencer: Sequencer_7 transitions_per_cycle: 32 -Cache config: l1u_0 +L2Cache_Controller config: L2CacheController_0 + version: 0 + buffer_size: 32 + cache: l2u_0 + number_of_TBEs: 256 + recycle_latency: 10 + request_latency: 14 + response_latency: 14 + transitions_per_cycle: 32 +L2Cache_Controller config: L2CacheController_1 + version: 1 + buffer_size: 32 + cache: l2u_1 + number_of_TBEs: 256 + recycle_latency: 10 + request_latency: 14 + response_latency: 14 + transitions_per_cycle: 32 +Cache config: l1d_0 controller: L1CacheController_0 - cache_associativity: 2 - num_cache_sets_bits: 1 - num_cache_sets: 2 - cache_set_size_bytes: 128 - cache_set_size_Kbytes: 0.125 - cache_set_size_Mbytes: 0.00012207 - cache_size_bytes: 256 - cache_size_Kbytes: 0.25 - cache_size_Mbytes: 0.000244141 -Cache config: l1u_1 + cache_associativity: 8 + num_cache_sets_bits: 4 + num_cache_sets: 16 + cache_set_size_bytes: 1024 + cache_set_size_Kbytes: 1 + cache_set_size_Mbytes: 0.000976562 + cache_size_bytes: 8192 + cache_size_Kbytes: 8 + cache_size_Mbytes: 0.0078125 +Cache config: l1d_1 controller: L1CacheController_1 - cache_associativity: 2 - num_cache_sets_bits: 1 - num_cache_sets: 2 - cache_set_size_bytes: 128 - cache_set_size_Kbytes: 0.125 - cache_set_size_Mbytes: 0.00012207 - cache_size_bytes: 256 - cache_size_Kbytes: 0.25 - cache_size_Mbytes: 0.000244141 -Cache config: l1u_2 + cache_associativity: 8 + num_cache_sets_bits: 4 + num_cache_sets: 16 + cache_set_size_bytes: 1024 + cache_set_size_Kbytes: 1 + cache_set_size_Mbytes: 0.000976562 + cache_size_bytes: 8192 + cache_size_Kbytes: 8 + cache_size_Mbytes: 0.0078125 +Cache config: l1d_2 controller: L1CacheController_2 - cache_associativity: 2 - num_cache_sets_bits: 1 - num_cache_sets: 2 - cache_set_size_bytes: 128 - cache_set_size_Kbytes: 0.125 - cache_set_size_Mbytes: 0.00012207 - cache_size_bytes: 256 - cache_size_Kbytes: 0.25 - cache_size_Mbytes: 0.000244141 -Cache config: l1u_3 + cache_associativity: 8 + num_cache_sets_bits: 4 + num_cache_sets: 16 + cache_set_size_bytes: 1024 + cache_set_size_Kbytes: 1 + cache_set_size_Mbytes: 0.000976562 + cache_size_bytes: 8192 + cache_size_Kbytes: 8 + cache_size_Mbytes: 0.0078125 +Cache config: l1d_3 controller: L1CacheController_3 - cache_associativity: 2 - num_cache_sets_bits: 1 - num_cache_sets: 2 - cache_set_size_bytes: 128 - cache_set_size_Kbytes: 0.125 - cache_set_size_Mbytes: 0.00012207 - cache_size_bytes: 256 - cache_size_Kbytes: 0.25 - cache_size_Mbytes: 0.000244141 -Cache config: l1u_4 + cache_associativity: 8 + num_cache_sets_bits: 4 + num_cache_sets: 16 + cache_set_size_bytes: 1024 + cache_set_size_Kbytes: 1 + cache_set_size_Mbytes: 0.000976562 + cache_size_bytes: 8192 + cache_size_Kbytes: 8 + cache_size_Mbytes: 0.0078125 +Cache config: l1d_4 controller: L1CacheController_4 - cache_associativity: 2 - num_cache_sets_bits: 1 - num_cache_sets: 2 - cache_set_size_bytes: 128 - cache_set_size_Kbytes: 0.125 - cache_set_size_Mbytes: 0.00012207 - cache_size_bytes: 256 - cache_size_Kbytes: 0.25 - cache_size_Mbytes: 0.000244141 -Cache config: l1u_5 + cache_associativity: 8 + num_cache_sets_bits: 4 + num_cache_sets: 16 + cache_set_size_bytes: 1024 + cache_set_size_Kbytes: 1 + cache_set_size_Mbytes: 0.000976562 + cache_size_bytes: 8192 + cache_size_Kbytes: 8 + cache_size_Mbytes: 0.0078125 +Cache config: l1d_5 controller: L1CacheController_5 - cache_associativity: 2 - num_cache_sets_bits: 1 - num_cache_sets: 2 - cache_set_size_bytes: 128 - cache_set_size_Kbytes: 0.125 - cache_set_size_Mbytes: 0.00012207 - cache_size_bytes: 256 - cache_size_Kbytes: 0.25 - cache_size_Mbytes: 0.000244141 -Cache config: l1u_6 + cache_associativity: 8 + num_cache_sets_bits: 4 + num_cache_sets: 16 + cache_set_size_bytes: 1024 + cache_set_size_Kbytes: 1 + cache_set_size_Mbytes: 0.000976562 + cache_size_bytes: 8192 + cache_size_Kbytes: 8 _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
