changeset 775342cda4db in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=775342cda4db
description:
ruby: removed last level cache support
Removed the last level cache support and MOESI_hammer's dependency on
it.
Replaces the LLC support with the more generic MachineType count.
diffstat:
7 files changed, 9 insertions(+), 43 deletions(-)
src/mem/protocol/MOESI_hammer-cache.sm | 4 +-
src/mem/protocol/MOESI_hammer-dir.sm | 4 +-
src/mem/protocol/RubySlicc_ComponentMapping.sm | 2 -
src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.cc | 4 --
src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh | 7 ++-
src/mem/ruby/system/CacheMemory.cc | 23 ------------
src/mem/ruby/system/CacheMemory.hh | 8 ----
diffs (168 lines):
diff -r a27441e3d106 -r 775342cda4db src/mem/protocol/MOESI_hammer-cache.sm
--- a/src/mem/protocol/MOESI_hammer-cache.sm Fri Jan 29 20:29:33 2010 -0800
+++ b/src/mem/protocol/MOESI_hammer-cache.sm Fri Jan 29 20:29:34 2010 -0800
@@ -379,7 +379,7 @@
out_msg.Requestor := machineID;
out_msg.Destination.add(map_Address_to_Directory(address));
out_msg.MessageSize := MessageSizeType:Request_Control;
- TBEs[address].NumPendingMsgs := getNumberOfLastLevelCaches(); // One
from each other cache (n-1) plus the memory (+1)
+ TBEs[address].NumPendingMsgs := machineCount(MachineType:L1Cache); //
One from each other cache (n-1) plus the memory (+1)
}
}
@@ -390,7 +390,7 @@
out_msg.Requestor := machineID;
out_msg.Destination.add(map_Address_to_Directory(address));
out_msg.MessageSize := MessageSizeType:Request_Control;
- TBEs[address].NumPendingMsgs := getNumberOfLastLevelCaches(); // One
from each other cache (n-1) plus the memory (+1)
+ TBEs[address].NumPendingMsgs := machineCount(MachineType:L1Cache); //
One from each other cache (n-1) plus the memory (+1)
}
}
diff -r a27441e3d106 -r 775342cda4db src/mem/protocol/MOESI_hammer-dir.sm
--- a/src/mem/protocol/MOESI_hammer-dir.sm Fri Jan 29 20:29:33 2010 -0800
+++ b/src/mem/protocol/MOESI_hammer-dir.sm Fri Jan 29 20:29:34 2010 -0800
@@ -320,7 +320,7 @@
//
// One ack for each last-level cache
//
- TBEs[address].NumPendingMsgs := getNumberOfLastLevelCaches();
+ TBEs[address].NumPendingMsgs := machineCount(MachineType:L1Cache);
//
// Assume initially that the caches store a clean copy and that memory
// will provide the data
@@ -468,7 +468,7 @@
}
action(f_forwardRequest, "f", desc="Forward requests") {
- if (getNumberOfLastLevelCaches() > 1) {
+ if (machineCount(MachineType:L1Cache) > 1) {
peek(requestQueue_in, RequestMsg) {
enqueue(forwardNetwork_out, RequestMsg,
latency=memory_controller_latency) {
out_msg.Address := address;
diff -r a27441e3d106 -r 775342cda4db
src/mem/protocol/RubySlicc_ComponentMapping.sm
--- a/src/mem/protocol/RubySlicc_ComponentMapping.sm Fri Jan 29 20:29:33
2010 -0800
+++ b/src/mem/protocol/RubySlicc_ComponentMapping.sm Fri Jan 29 20:29:34
2010 -0800
@@ -29,7 +29,7 @@
// Mapping functions
-int getNumberOfLastLevelCaches();
+int machineCount(MachineType machType);
// NodeID map_address_to_node(Address addr);
MachineID mapAddressToRange(Address addr, MachineType type, int low, int high);
diff -r a27441e3d106 -r 775342cda4db
src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.cc
--- a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.cc Fri Jan
29 20:29:33 2010 -0800
+++ b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.cc Fri Jan
29 20:29:34 2010 -0800
@@ -31,8 +31,4 @@
#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
#include "mem/ruby/system/CacheMemory.hh"
-int getNumberOfLastLevelCaches()
-{
- return CacheMemory::numberOfLastLevelCaches();
-}
diff -r a27441e3d106 -r 775342cda4db
src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
--- a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh Fri Jan
29 20:29:33 2010 -0800
+++ b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh Fri Jan
29 20:29:34 2010 -0800
@@ -42,6 +42,7 @@
#include "mem/ruby/common/NetDest.hh"
#include "mem/protocol/GenericMachineType.hh"
#include "mem/ruby/system/DirectoryMemory.hh"
+#include "mem/protocol/MachineType.hh"
#ifdef MACHINETYPE_L1Cache
#define MACHINETYPE_L1CACHE_ENUM MachineType_L1Cache
@@ -67,9 +68,6 @@
#define MACHINETYPE_DMA_ENUM MachineType_NUM
#endif
-// used to determine the number of acks to wait for
-int getNumberOfLastLevelCaches();
-
// used to determine the home directory
// returns a value between 0 and total_directories_within_the_system
inline
@@ -152,5 +150,8 @@
}
}
+extern inline int machineCount(MachineType machType) {
+ return MachineType_base_count(machType);
+}
#endif // COMPONENTMAPPINGFNS_H
diff -r a27441e3d106 -r 775342cda4db src/mem/ruby/system/CacheMemory.cc
--- a/src/mem/ruby/system/CacheMemory.cc Fri Jan 29 20:29:33 2010 -0800
+++ b/src/mem/ruby/system/CacheMemory.cc Fri Jan 29 20:29:34 2010 -0800
@@ -28,9 +28,6 @@
#include "mem/ruby/system/CacheMemory.hh"
-int CacheMemory::m_num_last_level_caches = 0;
-MachineType CacheMemory::m_last_level_machine_type = MachineType_FIRST;
-
// ******************* Definitions *******************
// Output operator definition
@@ -75,19 +72,6 @@
else
assert(false);
- m_num_last_level_caches =
- MachineType_base_count(MachineType_FIRST);
-#if 0
- for (uint32 i=0; i<argv.size(); i+=2) {
- if (m_last_level_machine_type < m_controller->getMachineType()) {
- m_num_last_level_caches =
- MachineType_base_count(m_controller->getMachineType());
- m_last_level_machine_type =
- m_controller->getMachineType();
- }
- }
-#endif
-
m_cache.setSize(m_cache_num_sets);
m_locked.setSize(m_cache_num_sets);
for (int i = 0; i < m_cache_num_sets; i++) {
@@ -112,13 +96,6 @@
}
}
-int
-CacheMemory::numberOfLastLevelCaches()
-{
- return m_num_last_level_caches;
-}
-
-
void CacheMemory::printConfig(ostream& out)
{
out << "Cache config: " << m_cache_name << endl;
diff -r a27441e3d106 -r 775342cda4db src/mem/ruby/system/CacheMemory.hh
--- a/src/mem/ruby/system/CacheMemory.hh Fri Jan 29 20:29:33 2010 -0800
+++ b/src/mem/ruby/system/CacheMemory.hh Fri Jan 29 20:29:34 2010 -0800
@@ -106,8 +106,6 @@
AccessPermission getPermission(const Address& address) const;
void changePermission(const Address& address, AccessPermission new_perm);
- static int numberOfLastLevelCaches();
-
int getLatency() const { return m_latency; }
// Hook for checkpointing the contents of the cache
@@ -172,12 +170,6 @@
int m_cache_num_sets;
int m_cache_num_set_bits;
int m_cache_assoc;
-
- static Vector< CacheMemory* > m_all_caches;
-
- static int m_num_last_level_caches;
- static MachineType m_last_level_machine_type;
-
};
#endif //CACHEMEMORY_H
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