changeset fe210e4ce76d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=fe210e4ce76d
description:
inorder: add insts to cpu event
some events are going to need instruction data when they process, so
just
include the instruction in the event construction
diffstat:
2 files changed, 24 insertions(+), 21 deletions(-)
src/cpu/inorder/cpu.cc | 29 +++++++++++++++--------------
src/cpu/inorder/cpu.hh | 16 +++++++++-------
diffs (170 lines):
diff -r 02562dac0416 -r fe210e4ce76d src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Sun Jan 31 18:25:48 2010 -0500
+++ b/src/cpu/inorder/cpu.cc Sun Jan 31 18:26:03 2010 -0500
@@ -84,10 +84,10 @@
}
InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
- Fault fault, ThreadID _tid, unsigned _vpe)
+ Fault fault, ThreadID _tid, DynInstPtr inst)
: Event(CPU_Tick_Pri), cpu(_cpu)
{
- setEvent(e_type, fault, _tid, _vpe);
+ setEvent(e_type, fault, _tid, inst);
}
@@ -317,7 +317,7 @@
contextSwitch = false;
// Define dummy instructions and resource requests to be used.
- DynInstPtr dummyBufferInst = new InOrderDynInst(this, NULL, 0, 0);
+ dummyInst = new InOrderDynInst(this, NULL, 0, 0);
dummyReq = new ResourceRequest(resPool->getResource(0), NULL, 0, 0, 0, 0);
// Reset CPU to reset state.
@@ -570,7 +570,7 @@
InOrderCPU::trap(Fault fault, ThreadID tid, int delay)
{
//@ Squash Pipeline during TRAP
- scheduleCpuEvent(Trap, fault, tid, 0/*vpe*/, delay);
+ scheduleCpuEvent(Trap, fault, tid, dummyInst, delay);
}
void
@@ -581,9 +581,10 @@
void
InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
- ThreadID tid, unsigned vpe, unsigned delay)
+ ThreadID tid, DynInstPtr inst,
+ unsigned delay)
{
- CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, vpe);
+ CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, inst);
if (delay >= 0) {
DPRINTF(InOrderCPU, "Scheduling CPU Event (%s) for cycle %i.\n",
@@ -597,7 +598,7 @@
// Broadcast event to the Resource Pool
DynInstPtr dummy_inst =
new InOrderDynInst(this, NULL, getNextEventNum(), tid);
- resPool->scheduleEvent(c_event, dummy_inst, 0, 0, tid);
+ resPool->scheduleEvent(c_event, inst, 0, 0, tid);
}
inline bool
@@ -699,7 +700,7 @@
"Enabling of concurrent virtual processor execution",
vpe);
- scheduleCpuEvent(EnableVPEs, NoFault, 0/*tid*/, vpe);
+ scheduleCpuEvent(EnableVPEs, NoFault, 0/*tid*/, dummyInst);
}
void
@@ -725,7 +726,7 @@
"Disabling of concurrent virtual processor execution",
vpe);
- scheduleCpuEvent(DisableVPEs, NoFault, 0/*tid*/, vpe);
+ scheduleCpuEvent(DisableVPEs, NoFault, 0/*tid*/, dummyInst);
}
void
@@ -759,7 +760,7 @@
DPRINTF(InOrderCPU, "[vpe:%i]: Scheduling Enable Multithreading on "
"virtual processor %i", vpe);
- scheduleCpuEvent(EnableThreads, NoFault, 0/*tid*/, vpe);
+ scheduleCpuEvent(EnableThreads, NoFault, 0/*tid*/, dummyInst);
}
void
@@ -786,7 +787,7 @@
DPRINTF(InOrderCPU, "[tid:%i]: Scheduling Disable Multithreading on "
"virtual processor %i", tid, vpe);
- scheduleCpuEvent(DisableThreads, NoFault, tid, vpe);
+ scheduleCpuEvent(DisableThreads, NoFault, tid, dummyInst);
}
void
@@ -850,7 +851,7 @@
{
DPRINTF(InOrderCPU,"[tid:%i]: Activating ...\n", tid);
- scheduleCpuEvent(ActivateThread, NoFault, tid, 0/*vpe*/, delay);
+ scheduleCpuEvent(ActivateThread, NoFault, tid, dummyInst, delay);
// Be sure to signal that there's some activity so the CPU doesn't
// deschedule itself.
@@ -863,7 +864,7 @@
void
InOrderCPU::suspendContext(ThreadID tid, int delay)
{
- scheduleCpuEvent(SuspendThread, NoFault, tid, 0/*vpe*/, delay);
+ scheduleCpuEvent(SuspendThread, NoFault, tid, dummyInst, delay);
//_status = Idle;
}
@@ -877,7 +878,7 @@
void
InOrderCPU::deallocateContext(ThreadID tid, int delay)
{
- scheduleCpuEvent(DeallocateThread, NoFault, tid, 0/*vpe*/, delay);
+ scheduleCpuEvent(DeallocateThread, NoFault, tid, dummyInst, delay);
}
void
diff -r 02562dac0416 -r fe210e4ce76d src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hh Sun Jan 31 18:25:48 2010 -0500
+++ b/src/cpu/inorder/cpu.hh Sun Jan 31 18:26:03 2010 -0500
@@ -199,22 +199,24 @@
public:
CPUEventType cpuEventType;
ThreadID tid;
+ DynInstPtr inst;
+ Fault fault;
unsigned vpe;
- Fault fault;
-
+
public:
/** Constructs a CPU event. */
CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
- ThreadID _tid, unsigned _vpe);
+ ThreadID _tid, DynInstPtr inst);
/** Set Type of Event To Be Scheduled */
void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
- unsigned _vpe)
+ DynInstPtr _inst)
{
fault = _fault;
cpuEventType = e_type;
tid = _tid;
- vpe = _vpe;
+ inst = _inst;
+ vpe = 0;
}
/** Processes a resource event. */
@@ -232,7 +234,7 @@
/** Schedule a CPU Event */
void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
- unsigned vpe, unsigned delay = 0);
+ DynInstPtr inst, unsigned delay = 0);
public:
/** Interface between the CPU and CPU resources. */
@@ -240,7 +242,7 @@
/** Instruction used to signify that there is no *real* instruction in
buffer slot */
- DynInstPtr dummyBufferInst;
+ DynInstPtr dummyInst;
/** Used by resources to signify a denied access to a resource. */
ResourceRequest *dummyReq;
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