changeset 4eb9b3a25a6c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4eb9b3a25a6c
description:
inorder: mem. mgmt. update
update address List and address Map to take
into account multiple threads
diffstat:
2 files changed, 13 insertions(+), 9 deletions(-)
src/cpu/inorder/resources/cache_unit.cc | 18 +++++++++++-------
src/cpu/inorder/resources/cache_unit.hh | 4 ++--
diffs (77 lines):
diff -r c7e00670d83e -r 4eb9b3a25a6c src/cpu/inorder/resources/cache_unit.cc
--- a/src/cpu/inorder/resources/cache_unit.cc Sun Jan 31 18:27:02 2010 -0500
+++ b/src/cpu/inorder/resources/cache_unit.cc Sun Jan 31 18:27:12 2010 -0500
@@ -131,6 +131,8 @@
int
CacheUnit::getSlot(DynInstPtr inst)
{
+ ThreadID tid = inst->readTid();
+
if (tlbBlocked[inst->threadNumber]) {
return -1;
}
@@ -142,7 +144,7 @@
Addr req_addr = inst->getMemAddr();
if (resName == "icache_port" ||
- find(addrList.begin(), addrList.end(), req_addr) == addrList.end()) {
+ find(addrList[tid].begin(), addrList[tid].end(), req_addr) ==
addrList[tid].end()) {
int new_slot = Resource::getSlot(inst);
@@ -150,8 +152,8 @@
return -1;
inst->memTime = curTick;
- addrList.push_back(req_addr);
- addrMap[req_addr] = inst->seqNum;
+ addrList[tid].push_back(req_addr);
+ addrMap[tid][req_addr] = inst->seqNum;
DPRINTF(InOrderCachePort,
"[tid:%i]: [sn:%i]: Address %08p added to dependency list\n",
inst->readTid(), inst->seqNum, req_addr);
@@ -160,7 +162,7 @@
DPRINTF(InOrderCachePort,
"[tid:%i] Denying request because there is an outstanding"
" request to/for addr. %08p. by [sn:%i] @ tick %i\n",
- inst->readTid(), req_addr, addrMap[req_addr], inst->memTime);
+ inst->readTid(), req_addr, addrMap[tid][req_addr],
inst->memTime);
return -1;
}
}
@@ -168,15 +170,17 @@
void
CacheUnit::freeSlot(int slot_num)
{
- vector<Addr>::iterator vect_it = find(addrList.begin(), addrList.end(),
+ ThreadID tid = reqMap[slot_num]->inst->readTid();
+
+ vector<Addr>::iterator vect_it = find(addrList[tid].begin(),
addrList[tid].end(),
reqMap[slot_num]->inst->getMemAddr());
- assert(vect_it != addrList.end());
+ assert(vect_it != addrList[tid].end());
DPRINTF(InOrderCachePort,
"[tid:%i]: Address %08p removed from dependency list\n",
reqMap[slot_num]->inst->readTid(), (*vect_it));
- addrList.erase(vect_it);
+ addrList[tid].erase(vect_it);
Resource::freeSlot(slot_num);
}
diff -r c7e00670d83e -r 4eb9b3a25a6c src/cpu/inorder/resources/cache_unit.hh
--- a/src/cpu/inorder/resources/cache_unit.hh Sun Jan 31 18:27:02 2010 -0500
+++ b/src/cpu/inorder/resources/cache_unit.hh Sun Jan 31 18:27:12 2010 -0500
@@ -198,9 +198,9 @@
bool cacheBlocked;
- std::vector<Addr> addrList;
+ std::vector<Addr> addrList[ThePipeline::MaxThreads];
- std::map<Addr, InstSeqNum> addrMap;
+ std::map<Addr, InstSeqNum> addrMap[ThePipeline::MaxThreads];
public:
int cacheBlkSize;
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