changeset 17801e070302 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=17801e070302
description:
inorder: ready thread wakeup
allow a thread to wakeup and be activated after
it has been in suspended state and another
thread is switched out. Need to give
pipeline stages a "activateThread" function
so that can get to their suspended instruction
when the time is right.
diffstat:
5 files changed, 51 insertions(+), 3 deletions(-)
src/cpu/inorder/cpu.cc | 14 +++++++++++++-
src/cpu/inorder/cpu.hh | 3 ++-
src/cpu/inorder/pipeline_stage.cc | 30 ++++++++++++++++++++++++++++++
src/cpu/inorder/pipeline_stage.hh | 2 ++
src/cpu/inorder/resources/cache_unit.cc | 5 ++++-
diffs (142 lines):
diff -r 6e0d37136836 -r 17801e070302 src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Sun Jan 31 18:27:25 2010 -0500
+++ b/src/cpu/inorder/cpu.cc Sun Jan 31 18:27:38 2010 -0500
@@ -674,6 +674,8 @@
DPRINTF(InOrderCPU,
"Attempting to activate new thread, but No Ready Threads to"
"activate.\n");
+ DPRINTF(InOrderCPU,
+ "Unable to switch to next active thread.\n");
}
}
@@ -696,7 +698,7 @@
"Ignoring activation of [tid:%i], since [tid:%i] is "
"already running.\n", tid, activeThreadId());
- DPRINTF(InOrderCPU,"Placing [tid:%i] ready threads list\n",
+ DPRINTF(InOrderCPU,"Placing [tid:%i] on ready threads list\n",
tid);
readyThreads.push_back(tid);
@@ -706,11 +708,21 @@
"Adding [tid:%i] to active threads list.\n", tid);
activeThreads.push_back(tid);
+ activateThreadInPipeline(tid);
+
wakeCPU();
}
}
void
+InOrderCPU::activateThreadInPipeline(ThreadID tid)
+{
+ for (int stNum=0; stNum < NumStages; stNum++) {
+ pipelineStage[stNum]->activateThread(tid);
+ }
+}
+
+void
InOrderCPU::deactivateContext(ThreadID tid, int delay)
{
DPRINTF(InOrderCPU,"[tid:%i]: Deactivating ...\n", tid);
diff -r 6e0d37136836 -r 17801e070302 src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hh Sun Jan 31 18:27:25 2010 -0500
+++ b/src/cpu/inorder/cpu.hh Sun Jan 31 18:27:38 2010 -0500
@@ -346,7 +346,8 @@
/** Add Thread to Active Threads List. */
void activateContext(ThreadID tid, int delay = 0);
void activateThread(ThreadID tid);
-
+ void activateThreadInPipeline(ThreadID tid);
+
/** Add Thread to Active Threads List. */
void activateNextReadyContext(int delay = 0);
void activateNextReadyThread();
diff -r 6e0d37136836 -r 17801e070302 src/cpu/inorder/pipeline_stage.cc
--- a/src/cpu/inorder/pipeline_stage.cc Sun Jan 31 18:27:25 2010 -0500
+++ b/src/cpu/inorder/pipeline_stage.cc Sun Jan 31 18:27:38 2010 -0500
@@ -558,6 +558,28 @@
}
}
+void
+PipelineStage::activateThread(ThreadID tid)
+{
+ if (cpu->threadModel == InOrderCPU::SwitchOnCacheMiss) {
+ if (!switchedOutValid[tid]) {
+ DPRINTF(InOrderStage, "[tid:%i] No instruction available in "
+ "switch out buffer.\n", tid);
+ } else {
+ DynInstPtr inst = switchedOutBuffer[tid];
+
+ DPRINTF(InOrderStage,"[tid:%i]: Re-Inserting [sn:%lli] PC:%#x into
stage skidBuffer %i\n",
+ tid, inst->seqNum, inst->readPC(), inst->threadNumber);
+
+ skidBuffer[tid].push(inst);
+
+ switchedOutBuffer[tid] = NULL;
+
+ switchedOutValid[tid] = false;
+ }
+ }
+
+}
void
@@ -945,6 +967,11 @@
if (req->isMemStall() &&
cpu->threadModel == InOrderCPU::SwitchOnCacheMiss) {
// Save Stalling Instruction
+ DPRINTF(ThreadModel, "[tid:%i] Detected cache miss.\n",
tid);
+
+ DPRINTF(InOrderStage, "Inserting [tid:%i][sn:%i] into
switch out buffer.\n",
+ tid, inst->seqNum);
+
switchedOutBuffer[tid] = inst;
switchedOutValid[tid] = true;
@@ -956,9 +983,12 @@
// Switch On Cache Miss
//=====================
// Suspend Thread at end of cycle
+ DPRINTF(ThreadModel, "Suspending [tid:%i] due to cache
miss.\n", tid);
cpu->suspendContext(tid);
// Activate Next Ready Thread at end of cycle
+ DPRINTF(ThreadModel, "Attempting to activate next ready
thread due to"
+ " cache miss.\n");
cpu->activateNextReadyContext();
}
diff -r 6e0d37136836 -r 17801e070302 src/cpu/inorder/pipeline_stage.hh
--- a/src/cpu/inorder/pipeline_stage.hh Sun Jan 31 18:27:25 2010 -0500
+++ b/src/cpu/inorder/pipeline_stage.hh Sun Jan 31 18:27:38 2010 -0500
@@ -235,6 +235,8 @@
public:
+ virtual void activateThread(ThreadID tid);
+
/** Squashes if there is a PC-relative branch that was predicted
* incorrectly. Sends squash information back to fetch.
*/
diff -r 6e0d37136836 -r 17801e070302 src/cpu/inorder/resources/cache_unit.cc
--- a/src/cpu/inorder/resources/cache_unit.cc Sun Jan 31 18:27:25 2010 -0500
+++ b/src/cpu/inorder/resources/cache_unit.cc Sun Jan 31 18:27:38 2010 -0500
@@ -708,9 +708,12 @@
if (cache_req->isMemStall() &&
cpu->threadModel == InOrderCPU::SwitchOnCacheMiss) {
- DPRINTF(InOrderCachePort, "[tid:%u] Waking up from Cache Miss.\n");
+ DPRINTF(InOrderCachePort, "[tid:%u] Waking up from Cache Miss.\n",
tid);
cpu->activateContext(tid);
+
+ DPRINTF(ThreadModel, "Activating [tid:%i] after return from cache"
+ "miss.\n", tid);
}
// Wake up the CPU (if it went to sleep and was waiting on this
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