changeset 96b33f6f9b7d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=96b33f6f9b7d
description:
inorder: ctxt switch stats
- m5 line enforcement on use_def.cc,hh
diffstat:
6 files changed, 194 insertions(+), 66 deletions(-)
src/cpu/inorder/cpu.cc | 26 +++
src/cpu/inorder/cpu.hh | 5
src/cpu/inorder/pipeline_stage.cc | 3
src/cpu/inorder/resources/graduation_unit.hh | 2
src/cpu/inorder/resources/use_def.cc | 212 ++++++++++++++++++--------
src/cpu/inorder/resources/use_def.hh | 12 +
diffs (truncated from 492 to 300 lines):
diff -r 16d59c27bd01 -r 96b33f6f9b7d src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Sun Jan 31 18:28:51 2010 -0500
+++ b/src/cpu/inorder/cpu.cc Sun Jan 31 18:28:59 2010 -0500
@@ -189,7 +189,8 @@
#endif // DEBUG
switchCount(0),
deferRegistration(false/*params->deferRegistration*/),
- stageTracing(params->stageTracing)
+ stageTracing(params->stageTracing),
+ instsPerSwitch(0)
{
ThreadID active_threads;
cpu_params = params;
@@ -352,6 +353,15 @@
}
/* Register any of the InOrderCPU's stats here.*/
+ instsPerCtxtSwitch
+ .name(name() + ".instsPerContextSwitch")
+ .desc("Instructions Committed Per Context Switch")
+ .prereq(instsPerCtxtSwitch);
+
+ numCtxtSwitches
+ .name(name() + ".contextSwitches")
+ .desc("Number of context switches");
+
timesIdled
.name(name() + ".timesIdled")
.desc("Number of times that the entire CPU went into an idle state and"
@@ -719,6 +729,8 @@
tcBase(tid)->setStatus(ThreadContext::Active);
wakeCPU();
+
+ numCtxtSwitches++;
}
}
@@ -1056,6 +1068,15 @@
return --(instList[tid].end());
}
+void
+InOrderCPU::updateContextSwitchStats()
+{
+ // Set Average Stat Here, then reset to 0
+ instsPerCtxtSwitch = instsPerSwitch;
+ instsPerSwitch = 0;
+}
+
+
void
InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
{
@@ -1086,6 +1107,9 @@
inst->traceData = NULL;
}
+ // Increment active thread's instruction count
+ instsPerSwitch++;
+
// Increment thread-state's instruction count
thread[tid]->numInst++;
diff -r 16d59c27bd01 -r 96b33f6f9b7d src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hh Sun Jan 31 18:28:51 2010 -0500
+++ b/src/cpu/inorder/cpu.hh Sun Jan 31 18:28:59 2010 -0500
@@ -707,6 +707,11 @@
/** The cycle that the CPU was last running, used for statistics. */
Tick lastRunningCycle;
+ void updateContextSwitchStats();
+ unsigned instsPerSwitch;
+ Stats::Average instsPerCtxtSwitch;
+ Stats::Scalar numCtxtSwitches;
+
/** Update Thread , used for statistic purposes*/
inline void tickThreadStats();
diff -r 16d59c27bd01 -r 96b33f6f9b7d src/cpu/inorder/pipeline_stage.cc
--- a/src/cpu/inorder/pipeline_stage.cc Sun Jan 31 18:28:51 2010 -0500
+++ b/src/cpu/inorder/pipeline_stage.cc Sun Jan 31 18:28:59 2010 -0500
@@ -570,6 +570,9 @@
// Clear switchout buffer
switchedOutBuffer[tid] = NULL;
switchedOutValid[tid] = false;
+
+ // Update any CPU stats based off context switches
+ cpu->updateContextSwitchStats();
}
}
diff -r 16d59c27bd01 -r 96b33f6f9b7d
src/cpu/inorder/resources/graduation_unit.hh
--- a/src/cpu/inorder/resources/graduation_unit.hh Sun Jan 31 18:28:51
2010 -0500
+++ b/src/cpu/inorder/resources/graduation_unit.hh Sun Jan 31 18:28:59
2010 -0500
@@ -63,8 +63,6 @@
bool *nonSpecInstActive[ThePipeline::MaxThreads];
InstSeqNum *nonSpecSeqNum[ThePipeline::MaxThreads];
-
- /** @todo: Add Resource Stats Here */
};
#endif //__CPU_INORDER_GRAD_UNIT_HH__
diff -r 16d59c27bd01 -r 96b33f6f9b7d src/cpu/inorder/resources/use_def.cc
--- a/src/cpu/inorder/resources/use_def.cc Sun Jan 31 18:28:51 2010 -0500
+++ b/src/cpu/inorder/resources/use_def.cc Sun Jan 31 18:28:59 2010 -0500
@@ -59,6 +59,17 @@
}
+void
+UseDefUnit::regStats()
+{
+ uniqueRegsPerSwitch
+ .name(name() + ".uniqueRegsPerSwitch")
+ .desc("Number of Unique Registers Needed Per Context Switch")
+ .prereq(uniqueRegsPerSwitch);
+
+ Resource::regStats();
+}
+
ResReqPtr
UseDefUnit::getRequest(DynInstPtr inst, int stage_num, int res_idx,
int slot_num, unsigned cmd)
@@ -75,7 +86,8 @@
map<int, ResReqPtr>::iterator map_end = reqMap.end();
while (map_it != map_end) {
- UseDefRequest* ud_req = dynamic_cast<UseDefRequest*>((*map_it).second);
+ UseDefRequest* ud_req =
+ dynamic_cast<UseDefRequest*>((*map_it).second);
assert(ud_req);
if (ud_req &&
@@ -107,9 +119,9 @@
// in the pipeline then stall instructions here
if (*nonSpecInstActive[tid] == true &&
seq_num > *nonSpecSeqNum[tid]) {
- DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i] cannot execute because there
is "
- "non-speculative instruction [sn:%i] has not graduated.\n",
- tid, seq_num, *nonSpecSeqNum[tid]);
+ DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i] cannot execute because"
+ "there is non-speculative instruction [sn:%i] has not "
+ "graduated.\n", tid, seq_num, *nonSpecSeqNum[tid]);
return;
} else if (inst->isNonSpeculative()) {
*nonSpecInstActive[tid] = true;
@@ -121,89 +133,129 @@
case ReadSrcReg:
{
int reg_idx = inst->_srcRegIdx[ud_idx];
-
- DPRINTF(InOrderUseDef, "[tid:%i]: Attempting to read source
register idx %i (reg #%i).\n",
+
+ DPRINTF(InOrderUseDef, "[tid:%i]: Attempting to read source "
+ "register idx %i (reg #%i).\n",
tid, ud_idx, reg_idx);
- // Ask register dependency map if it is OK to read from Arch. Reg.
File
+ // Ask register dependency map if it is OK to read from Arch.
+ // Reg. File
if (regDepMap[tid]->canRead(reg_idx, inst)) {
+
+ uniqueRegMap[reg_idx] = true;
+
if (inst->seqNum <= outReadSeqNum[tid]) {
if (reg_idx < FP_Base_DepTag) {
- DPRINTF(InOrderUseDef, "[tid:%i]: Reading Int Reg %i
from Register File:%i.\n",
- tid, reg_idx,
cpu->readIntReg(reg_idx,inst->readTid()));
+ DPRINTF(InOrderUseDef, "[tid:%i]: Reading Int Reg %i"
+ "from Register File:%i.\n",
+ tid,
+ reg_idx,
+ cpu->readIntReg(reg_idx,inst->readTid()));
inst->setIntSrc(ud_idx,
-
cpu->readIntReg(reg_idx,inst->readTid()));
+ cpu->readIntReg(reg_idx,
+ inst->readTid()));
} else if (reg_idx < Ctrl_Base_DepTag) {
reg_idx -= FP_Base_DepTag;
- DPRINTF(InOrderUseDef, "[tid:%i]: Reading Float Reg %i
from Register File:%x (%08f).\n",
+ DPRINTF(InOrderUseDef, "[tid:%i]: Reading Float Reg %i"
+ "from Register File:%x (%08f).\n",
tid,
reg_idx,
- cpu->readFloatRegBits(reg_idx,
inst->readTid()),
- cpu->readFloatReg(reg_idx, inst->readTid()));
+ cpu->readFloatRegBits(reg_idx,
+ inst->readTid()),
+ cpu->readFloatReg(reg_idx,
+ inst->readTid()));
inst->setFloatSrc(ud_idx,
- cpu->readFloatReg(reg_idx,
inst->readTid()));
+ cpu->readFloatReg(reg_idx,
+ inst->readTid()));
} else {
reg_idx -= Ctrl_Base_DepTag;
- DPRINTF(InOrderUseDef, "[tid:%i]: Reading Misc Reg %i
from Register File:%i.\n",
- tid, reg_idx, cpu->readMiscReg(reg_idx,
inst->readTid()));
+ DPRINTF(InOrderUseDef, "[tid:%i]: Reading Misc Reg %i "
+ "from Register File:%i.\n",
+ tid,
+ reg_idx,
+ cpu->readMiscReg(reg_idx,
+ inst->readTid()));
inst->setIntSrc(ud_idx,
- cpu->readMiscReg(reg_idx,
inst->readTid()));
+ cpu->readMiscReg(reg_idx,
+ inst->readTid()));
}
outReadSeqNum[tid] = maxSeqNum;
ud_req->done();
} else {
- DPRINTF(InOrderUseDef, "[tid:%i]: Unable to read because
of [sn:%i] hasnt read it's"
- " registers yet.\n", tid, outReadSeqNum[tid]);
- DPRINTF(InOrderStall, "STALL: [tid:%i]: waiting for
[sn:%i] to write\n",
+ DPRINTF(InOrderUseDef, "[tid:%i]: Unable to read because "
+ "of [sn:%i] hasnt read it's registers yet.\n",
+ tid, outReadSeqNum[tid]);
+ DPRINTF(InOrderStall, "STALL: [tid:%i]: waiting for "
+ "[sn:%i] to write\n",
tid, outReadSeqNum[tid]);
}
} else {
// Look for forwarding opportunities
- DynInstPtr forward_inst = regDepMap[tid]->canForward(reg_idx,
ud_idx, inst);
+ DynInstPtr forward_inst = regDepMap[tid]->canForward(reg_idx,
+ ud_idx,
+ inst);
if (forward_inst) {
if (inst->seqNum <= outReadSeqNum[tid]) {
- int dest_reg_idx =
forward_inst->getDestIdxNum(reg_idx);
+ int dest_reg_idx =
+ forward_inst->getDestIdxNum(reg_idx);
if (reg_idx < FP_Base_DepTag) {
- DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest.
reg value 0x%x from "
+ DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest."
+ " reg value 0x%x from "
"[sn:%i] to [sn:%i] source #%i.\n",
- tid,
forward_inst->readIntResult(dest_reg_idx) ,
- forward_inst->seqNum, inst->seqNum,
ud_idx);
- inst->setIntSrc(ud_idx,
forward_inst->readIntResult(dest_reg_idx));
+ tid,
+ forward_inst->readIntResult(dest_reg_idx),
+ forward_inst->seqNum,
+ inst->seqNum, ud_idx);
+ inst->setIntSrc(ud_idx,
+ forward_inst->
+ readIntResult(dest_reg_idx));
} else if (reg_idx < Ctrl_Base_DepTag) {
- DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest.
reg value 0x%x from "
+ DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest."
+ " reg value 0x%x from "
"[sn:%i] to [sn:%i] source #%i.\n",
- tid,
forward_inst->readFloatResult(dest_reg_idx) ,
+ tid,
+
forward_inst->readFloatResult(dest_reg_idx),
forward_inst->seqNum, inst->seqNum,
ud_idx);
inst->setFloatSrc(ud_idx,
-
forward_inst->readFloatResult(dest_reg_idx));
+ forward_inst->
+ readFloatResult(dest_reg_idx));
} else {
- DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest.
reg value 0x%x from "
+ DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest."
+ " reg value 0x%x from "
"[sn:%i] to [sn:%i] source #%i.\n",
- tid,
forward_inst->readIntResult(dest_reg_idx) ,
- forward_inst->seqNum, inst->seqNum,
ud_idx);
- inst->setIntSrc(ud_idx,
forward_inst->readIntResult(dest_reg_idx));
+ tid,
+ forward_inst->readIntResult(dest_reg_idx),
+ forward_inst->seqNum,
+ inst->seqNum, ud_idx);
+ inst->setIntSrc(ud_idx,
+ forward_inst->
+ readIntResult(dest_reg_idx));
}
outReadSeqNum[tid] = maxSeqNum;
ud_req->done();
} else {
- DPRINTF(InOrderUseDef, "[tid:%i]: Unable to read
because of [sn:%i] hasnt read it's"
+ DPRINTF(InOrderUseDef, "[tid:%i]: Unable to read "
+ "because of [sn:%i] hasnt read it's"
" registers yet.\n", tid, outReadSeqNum[tid]);
- DPRINTF(InOrderStall, "STALL: [tid:%i]: waiting for
[sn:%i] to forward\n",
+ DPRINTF(InOrderStall, "STALL: [tid:%i]: waiting for "
+ "[sn:%i] to forward\n",
tid, outReadSeqNum[tid]);
}
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