changeset 6327f5071027 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6327f5071027
description:
inorder: user per-thread dummy insts/reqs
diffstat:
4 files changed, 30 insertions(+), 20 deletions(-)
src/cpu/inorder/cpu.cc | 35 +++++++++++++++++++++++++----------
src/cpu/inorder/cpu.hh | 7 +++++--
src/cpu/inorder/resource_pool.cc | 5 -----
src/cpu/inorder/resource_pool.hh | 3 ---
diffs (159 lines):
diff -r f44ba2f42b5c -r 6327f5071027 src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Sun Jan 31 18:29:49 2010 -0500
+++ b/src/cpu/inorder/cpu.cc Sun Jan 31 18:29:59 2010 -0500
@@ -211,6 +211,7 @@
"edit your workload size.");
}
+
if (active_threads > 1) {
threadModel = (InOrderCPU::ThreadModel) params->threadModel;
@@ -257,6 +258,9 @@
Process* dummy_proc = params->workload[0];
thread[tid] = new Thread(this, tid, dummy_proc);
}
+
+ // Eventually set this with parameters...
+ asid[tid] = tid;
#endif
// Setup the TC that will serve as the interface to the threads/CPU.
@@ -313,14 +317,24 @@
isa[tid].clear();
isa[tid].expandForMultithreading(numThreads, 1/*numVirtProcs*/);
+
+ // Define dummy instructions and resource requests to be used.
+ dummyInst[tid] = new InOrderDynInst(this,
+ thread[tid],
+ 0,
+ tid,
+ asid[tid]);
+
+ dummyReq[tid] = new ResourceRequest(resPool->getResource(0),
+ dummyInst[tid],
+ 0,
+ 0,
+ 0,
+ 0);
}
lastRunningCycle = curTick;
- // Define dummy instructions and resource requests to be used.
- dummyInst = new InOrderDynInst(this, NULL, 0, 0);
- dummyReq = new ResourceRequest(resPool->getResource(0), NULL, 0, 0, 0, 0);
-
// Reset CPU to reset state.
#if FULL_SYSTEM
Fault resetFault = new ResetFault();
@@ -585,7 +599,7 @@
InOrderCPU::trap(Fault fault, ThreadID tid, int delay)
{
//@ Squash Pipeline during TRAP
- scheduleCpuEvent(Trap, fault, tid, dummyInst, delay);
+ scheduleCpuEvent(Trap, fault, tid, dummyInst[tid], delay);
}
void
@@ -747,7 +761,7 @@
{
DPRINTF(InOrderCPU,"[tid:%i]: Deactivating ...\n", tid);
- scheduleCpuEvent(DeactivateThread, NoFault, tid, dummyInst, delay);
+ scheduleCpuEvent(DeactivateThread, NoFault, tid, dummyInst[tid], delay);
// Be sure to signal that there's some activity so the CPU doesn't
// deschedule itself.
@@ -830,7 +844,8 @@
{
DPRINTF(InOrderCPU,"[tid:%i]: Activating ...\n", tid);
- scheduleCpuEvent(ActivateThread, NoFault, tid, dummyInst, delay);
+
+ scheduleCpuEvent(ActivateThread, NoFault, tid, dummyInst[tid], delay);
// Be sure to signal that there's some activity so the CPU doesn't
// deschedule itself.
@@ -847,7 +862,7 @@
// NOTE: Add 5 to the event priority so that we always activate
// threads after we've finished deactivating, squashing,etc.
// other threads
- scheduleCpuEvent(ActivateNextReadyThread, NoFault, 0/*tid*/, dummyInst,
+ scheduleCpuEvent(ActivateNextReadyThread, NoFault, 0/*tid*/, dummyInst[0],
delay, 5);
// Be sure to signal that there's some activity so the CPU doesn't
@@ -862,7 +877,7 @@
{
DPRINTF(InOrderCPU, "[tid:%i]: Calling Halt Context...\n", tid);
- scheduleCpuEvent(HaltThread, NoFault, tid, dummyInst, delay);
+ scheduleCpuEvent(HaltThread, NoFault, tid, dummyInst[tid], delay);
activityRec.activity();
}
@@ -885,7 +900,7 @@
void
InOrderCPU::suspendContext(ThreadID tid, int delay)
{
- scheduleCpuEvent(SuspendThread, NoFault, tid, dummyInst, delay);
+ scheduleCpuEvent(SuspendThread, NoFault, tid, dummyInst[tid], delay);
}
void
diff -r f44ba2f42b5c -r 6327f5071027 src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hh Sun Jan 31 18:29:49 2010 -0500
+++ b/src/cpu/inorder/cpu.hh Sun Jan 31 18:29:59 2010 -0500
@@ -97,6 +97,9 @@
/** CPU ID */
int cpu_id;
+ // SE Mode ASIDs
+ ThreadID asid[ThePipeline::MaxThreads];
+
/** Type of core that this is */
std::string coreType;
@@ -241,10 +244,10 @@
/** Instruction used to signify that there is no *real* instruction in
buffer slot */
- DynInstPtr dummyInst;
+ DynInstPtr dummyInst[ThePipeline::MaxThreads];
/** Used by resources to signify a denied access to a resource. */
- ResourceRequest *dummyReq;
+ ResourceRequest *dummyReq[ThePipeline::MaxThreads];
/** Identifies the resource id that identifies a fetch
* access unit.
diff -r f44ba2f42b5c -r 6327f5071027 src/cpu/inorder/resource_pool.cc
--- a/src/cpu/inorder/resource_pool.cc Sun Jan 31 18:29:49 2010 -0500
+++ b/src/cpu/inorder/resource_pool.cc Sun Jan 31 18:29:59 2010 -0500
@@ -448,11 +448,6 @@
}
}
-ResourcePool::ResPoolEvent::ResPoolEvent(ResourcePool *_resPool)
- : Event((Event::Priority)((unsigned)CPU_Tick_Pri+5)), resPool(_resPool),
- eventType((InOrderCPU::CPUEventType) Default)
-{ }
-
ResourcePool::ResPoolEvent::ResPoolEvent(ResourcePool *_resPool,
InOrderCPU::CPUEventType e_type,
DynInstPtr _inst,
diff -r f44ba2f42b5c -r 6327f5071027 src/cpu/inorder/resource_pool.hh
--- a/src/cpu/inorder/resource_pool.hh Sun Jan 31 18:29:49 2010 -0500
+++ b/src/cpu/inorder/resource_pool.hh Sun Jan 31 18:29:59 2010 -0500
@@ -86,9 +86,6 @@
public:
/** Constructs a resource event. */
- ResPoolEvent(ResourcePool *_resPool);
-
- /** Constructs a resource event. */
ResPoolEvent(ResourcePool *_resPool,
InOrderCPU::CPUEventType e_type,
DynInstPtr _inst,
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
