changeset 88555fd4d220 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=88555fd4d220
description:
inorder: implement split loads
diffstat:
8 files changed, 373 insertions(+), 40 deletions(-)
src/cpu/inorder/inorder_dyn_inst.cc | 10 -
src/cpu/inorder/inorder_dyn_inst.hh | 18 +
src/cpu/inorder/pipeline_traits.hh | 6
src/cpu/inorder/resource.cc | 13 +
src/cpu/inorder/resource_pool.cc | 19 +
src/cpu/inorder/resource_pool.hh | 1
src/cpu/inorder/resources/cache_unit.cc | 310 ++++++++++++++++++++++++++++---
src/cpu/inorder/resources/cache_unit.hh | 36 ++-
diffs (truncated from 756 to 300 lines):
diff -r 31ae0245e4ac -r 88555fd4d220 src/cpu/inorder/inorder_dyn_inst.cc
--- a/src/cpu/inorder/inorder_dyn_inst.cc Sun Jan 31 18:30:24 2010 -0500
+++ b/src/cpu/inorder/inorder_dyn_inst.cc Sun Jan 31 18:30:35 2010 -0500
@@ -111,7 +111,11 @@
{
fetchMemReq = NULL;
dataMemReq = NULL;
-
+ splitMemData = NULL;
+ split2ndAccess = false;
+ splitInst = false;
+ splitFinishCnt = 0;
+
effAddr = 0;
physEffAddr = 0;
@@ -187,6 +191,10 @@
delete traceData;
}
+ if (splitMemData) {
+ delete splitMemData;
+ }
+
fault = NoFault;
--instcount;
diff -r 31ae0245e4ac -r 88555fd4d220 src/cpu/inorder/inorder_dyn_inst.hh
--- a/src/cpu/inorder/inorder_dyn_inst.hh Sun Jan 31 18:30:24 2010 -0500
+++ b/src/cpu/inorder/inorder_dyn_inst.hh Sun Jan 31 18:30:35 2010 -0500
@@ -330,6 +330,19 @@
public:
Tick memTime;
+ PacketDataPtr splitMemData;
+ RequestPtr splitMemReq;
+ int splitTotalSize;
+ int split2ndSize;
+ Addr split2ndAddr;
+ bool split2ndAccess;
+ uint8_t split2ndData;
+ PacketDataPtr split2ndDataPtr;
+ unsigned split2ndFlags;
+ bool splitInst;
+ int splitFinishCnt;
+
+
////////////////////////////////////////////////////////////
//
// BASE INSTRUCTION INFORMATION.
@@ -468,7 +481,10 @@
if (!resSched.empty()) {
ThePipeline::ScheduleEntry* sked = resSched.top();
resSched.pop();
- delete sked;
+ if (sked != 0) {
+ delete sked;
+
+ }
}
}
diff -r 31ae0245e4ac -r 88555fd4d220 src/cpu/inorder/pipeline_traits.hh
--- a/src/cpu/inorder/pipeline_traits.hh Sun Jan 31 18:30:24 2010 -0500
+++ b/src/cpu/inorder/pipeline_traits.hh Sun Jan 31 18:30:35 2010 -0500
@@ -53,8 +53,8 @@
const unsigned StageWidth = 1;
const unsigned BackEndStartStage = 2;
- // Enumerated List of Resources The Pipeline Uses
- enum ResourceList {
+ // List of Resources The Pipeline Uses
+ enum ResourceId {
FetchSeq = 0,
ICache,
Decode,
@@ -94,6 +94,7 @@
stageNum(stage_num), resNum(res_num), cmd(_cmd),
idx(_idx), priority(_priority)
{ }
+
virtual ~ScheduleEntry(){}
// Stage number to perform this service.
@@ -159,7 +160,6 @@
stageNum, nextTaskPriority++, unit, request, param
));
}
-
};
};
diff -r 31ae0245e4ac -r 88555fd4d220 src/cpu/inorder/resource.cc
--- a/src/cpu/inorder/resource.cc Sun Jan 31 18:30:24 2010 -0500
+++ b/src/cpu/inorder/resource.cc Sun Jan 31 18:30:35 2010 -0500
@@ -262,15 +262,22 @@
map<int, ResReqPtr>::iterator map_it = reqMap.begin();
map<int, ResReqPtr>::iterator map_end = reqMap.end();
+ bool found = false;
+ ResReqPtr req = NULL;
+
while (map_it != map_end) {
if ((*map_it).second &&
- (*map_it).second->getInst() == inst) {
- return (*map_it).second;
+ (*map_it).second->getInst() == inst) {
+ req = (*map_it).second;
+ //return (*map_it).second;
+ assert(found == false);
+ found = true;
}
map_it++;
}
- return NULL;
+ return req;
+ //return NULL;
}
void
diff -r 31ae0245e4ac -r 88555fd4d220 src/cpu/inorder/resource_pool.cc
--- a/src/cpu/inorder/resource_pool.cc Sun Jan 31 18:30:24 2010 -0500
+++ b/src/cpu/inorder/resource_pool.cc Sun Jan 31 18:30:35 2010 -0500
@@ -181,6 +181,25 @@
return idx;
}
+ panic("Can't find resource idx for: %s\n", res_name);
+ return 0;
+}
+
+unsigned
+ResourcePool::getResIdx(const ThePipeline::ResourceId &res_id)
+{
+ int num_resources = resources.size();
+
+ for (int idx = 0; idx < num_resources; idx++) {
+ if (resources[idx]->getId() == res_id)
+ return idx;
+ }
+
+ // todo: change return value to int and return a -1 here
+ // maybe even have enumerated type
+ // panic for now...
+ panic("Can't find resource idx for: %i\n", res_id);
+
return 0;
}
diff -r 31ae0245e4ac -r 88555fd4d220 src/cpu/inorder/resource_pool.hh
--- a/src/cpu/inorder/resource_pool.hh Sun Jan 31 18:30:24 2010 -0500
+++ b/src/cpu/inorder/resource_pool.hh Sun Jan 31 18:30:35 2010 -0500
@@ -141,6 +141,7 @@
/** Returns a specific resource. */
unsigned getResIdx(const std::string &res_name);
+ unsigned getResIdx(const ThePipeline::ResourceId &res_id);
/** Returns a pointer to a resource */
Resource* getResource(int res_idx) { return resources[res_idx]; }
diff -r 31ae0245e4ac -r 88555fd4d220 src/cpu/inorder/resources/cache_unit.cc
--- a/src/cpu/inorder/resources/cache_unit.cc Sun Jan 31 18:30:24 2010 -0500
+++ b/src/cpu/inorder/resources/cache_unit.cc Sun Jan 31 18:30:35 2010 -0500
@@ -40,6 +40,7 @@
#include "cpu/inorder/resources/cache_unit.hh"
#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/inorder/cpu.hh"
+#include "cpu/inorder/resource_pool.hh"
#include "mem/request.hh"
using namespace std;
@@ -136,7 +137,9 @@
return -1;
}
- if (!inst->validMemAddr()) {
+ // For a Split-Load, the instruction would have processed once already
+ // causing the address to be unset.
+ if (!inst->validMemAddr() && !inst->splitInst) {
panic("Mem. Addr. must be set before requesting cache access\n");
}
@@ -159,12 +162,24 @@
inst->readTid(), inst->seqNum, req_addr);
return new_slot;
} else {
- DPRINTF(InOrderCachePort,
+ // Allow same instruction multiple accesses to same address
+ if (addrMap[tid][req_addr] == inst->seqNum) {
+ int new_slot = Resource::getSlot(inst);
+
+ if (new_slot == -1)
+ return -1;
+
+ return new_slot;
+ } else {
+ DPRINTF(InOrderCachePort,
"[tid:%i] Denying request because there is an outstanding"
" request to/for addr. %08p. by [sn:%i] @ tick %i\n",
inst->readTid(), req_addr, addrMap[tid][req_addr],
inst->memTime);
- return -1;
+ return -1;
+ }
}
+
+ return -1;
}
void
@@ -175,18 +190,70 @@
vector<Addr>::iterator vect_it =
find(addrList[tid].begin(), addrList[tid].end(),
reqMap[slot_num]->inst->getMemAddr());
- assert(vect_it != addrList[tid].end());
+
+ assert(vect_it != addrList[tid].end() ||
+ reqMap[slot_num]->inst->splitInst);
DPRINTF(InOrderCachePort,
"[tid:%i]: Address %08p removed from dependency list\n",
reqMap[slot_num]->inst->readTid(), (*vect_it));
- addrList[tid].erase(vect_it);
+ if (vect_it != addrList[tid].end()) {
+
+ DPRINTF(InOrderCachePort,
+ "[tid:%i]: Address %08p removed from dependency list\n",
+ reqMap[slot_num]->inst->readTid(), (*vect_it));
+
+ addrList[tid].erase(vect_it);
+ }
Resource::freeSlot(slot_num);
}
ResReqPtr
+CacheUnit::findRequest(DynInstPtr inst)
+{
+ map<int, ResReqPtr>::iterator map_it = reqMap.begin();
+ map<int, ResReqPtr>::iterator map_end = reqMap.end();
+
+ while (map_it != map_end) {
+ CacheRequest* cache_req =
dynamic_cast<CacheRequest*>((*map_it).second);
+ assert(cache_req);
+
+ if (cache_req &&
+ cache_req->getInst() == inst &&
+ cache_req->instIdx == inst->resSched.top()->idx) {
+ return cache_req;
+ }
+ map_it++;
+ }
+
+ return NULL;
+}
+
+ResReqPtr
+CacheUnit::findSplitRequest(DynInstPtr inst, int idx)
+{
+ map<int, ResReqPtr>::iterator map_it = reqMap.begin();
+ map<int, ResReqPtr>::iterator map_end = reqMap.end();
+
+ while (map_it != map_end) {
+ CacheRequest* cache_req =
dynamic_cast<CacheRequest*>((*map_it).second);
+ assert(cache_req);
+
+ if (cache_req &&
+ cache_req->getInst() == inst &&
+ cache_req->instIdx == idx) {
+ return cache_req;
+ }
+ map_it++;
+ }
+
+ return NULL;
+}
+
+
+ResReqPtr
CacheUnit::getRequest(DynInstPtr inst, int stage_num, int res_idx,
int slot_num, unsigned cmd)
{
@@ -200,6 +267,14 @@
switch (sched_entry->cmd)
{
+ case InitSecondSplitRead:
+ pkt_cmd = MemCmd::ReadReq;
+
+ DPRINTF(InOrderCachePort,
+ "[tid:%i]: Read request from [sn:%i] for addr %08p\n",
+ inst->readTid(), inst->seqNum, inst->split2ndAddr);
+ break;
+
case InitiateReadData:
pkt_cmd = MemCmd::ReadReq;
@@ -231,7 +306,8 @@
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